Article ID: 000080859 Content Type: Troubleshooting Last Reviewed: 10/31/2023

Riviera* Simulation Errors of the Intel® Stratix® 10 FPGA Avalon® Memory Mapped Interface for PCI Express* Solutions

Environment

  • Intel® Quartus® Prime Pro Edition
  • Avalon-ST Intel® Stratix® 10 Hard IP for PCI Express
  • Avalon-MM Intel® Stratix® 10 Hard IP+ for PCI Express
  • Avalon-MM Intel® Stratix® 10 Hard IP for PCI Express
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    Critical Issue

    Description

    Due to a problem wih the ALDEC* Riviera* simulation tool, the following or similar error will be seen when simulating the Intel® Stratix® 10 FPGA Avalon® Memory Mapped Interface for PCI Express* IP.

    SLPENFORCE: Fatal Error: AdvancedDcslOptimization.cpp (572): Internal fatal error

    Resolution

    No workaround is available when using the ALDEC* Riviera* simulation tool. This problem is not seen with other supported simulators.

    This problem has been reported to ALDEC*. A fix is scheduled for a future release of the ALDEC* Riviera* simulation tool.

    Related Products

    This article applies to 5 products

    Intel® Stratix® 10 MX FPGA
    Intel® Stratix® 10 TX FPGA
    Intel® Stratix® 10 FPGAs and SoC FPGAs
    Intel® Stratix® 10 GX FPGA
    Intel® Stratix® 10 SX SoC FPGA

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