Article ID: 000084239 Content Type: Troubleshooting Last Reviewed: 08/16/2012

Why does the Quartus II software fitter report sometimes show different PLL output counter ordering than what I have used in my design?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

When you instantiate a PLL in Arria® II, Cyclone® III, Cyclone IV, Stratix® III, and Stratix IV devices, you may find wire_pll1_clk[X] does not map to counter[X]. For example, you may find wire_pll1_clk[3] does not use C3 in the fitter report. That is expected behavior because the fitter will place PLL output clocks according to the required routing resources for the clock network.

 

If you want wire_pll1_clk[X] to dynamically phase shift, you will need to select the phasecounterselect for C[X] counter according to “Phase Counter Select Mapping” table in the device handbook. The phasecounterselect will be consistent with the RTL code, the physical mapping to output counter locations by the fitter is irrelevant.

Related Products

This article applies to 10 products

Stratix® III FPGAs
Arria® II GX FPGA
Arria® II GZ FPGA
Cyclone® III FPGAs
Cyclone® III LS FPGA
Cyclone® IV E FPGA
Cyclone® IV GX FPGA
Stratix® IV E FPGA
Stratix® IV GT FPGA
Stratix® IV GX FPGA