Description
LUT chains are a type of interconnect between consecutive combinatorial logic element (LE) functions. Like other interconnects, you cannot force the software to use this routing resource. The software automatically choses this routing by fitter critical paths when timing-driven compilation (TDC) is used.
You can guide register chain usage by using a WYSIWYG LE. There are regcascin and regcascout ports on the Stratix WYSIWYG LE that you can connect together in chain fashion as needed for up to one logic array block (LAB), or 10 LEs, in length. Otherwise, logic synthesis should take advantage of this automatically.