Due to a problem in the Quartus® II software, the Synopsys Design Constraint (SDC) command derive_pll_clocks may not properly constrain phase-locked loop (PLL) outputs. This problem occurs when your design uses PLL clock switchover in 28 nm devices, including Stratix® V, Arria® V, and Cyclone® V devices. Because of this problem, the derive_pll_clocks command does not automatically create the generated clocks on PLL outputs relative to each reference clock input.
To work around this problem, constrain the PLL outputs manually using create_generated_clock SDC commands. Refer to the Related Articles section for more details.
This problem is fixed starting with the Intel® Quartus® Prime Pro or Standard Edition Software version 11.0.