Article ID: 000084595 Content Type: Troubleshooting Last Reviewed: 02/08/2013

Elaboration errors might occur when using NC-Sim to perform post-fit VHDL functional simulations of designs that target Stratix V devices

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    If you use Cadence® NC-Sim to perform a post-fit VHDL functional simulation of a design that targets a member of the Stratix V family and that uses RAM, an elaboration error might occur if the component declaration parameters and the architecture parameters are out of order.

    Resolution

    Use the -namemap_mixgen option with the ncelab command to instruct NC-Sim to match the component declaration parameters and the architecture parameters based on names.

    Related Products

    This article applies to 1 products

    Stratix® V FPGAs