Article ID: 000084616 Content Type: Troubleshooting Last Reviewed: 02/09/2016

Why do I see random read errors when using the ALTDQ_DQS2 megafunction?

Environment

  • Intel® Quartus® Prime Standard Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the ALTDQ_DQS2 megafunction in the Quartus® II software, a glitch may occur at the output of the DQS logic block, which may cause random read errors when performing PVT testing. Your design is impacted if all three of the following conditions are true:

    1. The custom protocol is strobe-based, where the Make capture strobe bidirectional option is enabled in the ALTDQ_DQS2 MegaWizard™ GUI.


    2. The DQS enable block is used, where the Use capture strobe enable block option is enabled in the ALTDQ_DQS2 MegaWizard GUI (applicable for Arria® V GZ and Stratix® V families only).

    3. If the memory frequency is running in the affected range:

        • Cyclone® V E/GX/GT/SE/SX/ST & SoC: All frequencies

        • Arria® V GX/GT/SX/ST & SoC: All frequencies

        • Arria® V GZ: < 445MHz

        • Stratix® V (-1/-2 speed grade): <480MHz

        • Stratix® V (-3/-4 speed grade): <445MHz


    Resolution

    If your design is affected, Altera recommends the following workaround. Note that the Quartus software upgrade is needed for the workaround.

          • For Arria® V (except GZ) and Cyclone® V families: upgrade to Quartus software version 14.0 and newer

          • For Arria® V GZ and Stratix® V families: upgrade to Quartus software version 13.1 and newer

     

    Please refer to workaround in ALTDQ_DQS2_DQS_Logic_Block PDF file for your application.

     

    Related Products

    This article applies to 3 products

    Arria® V FPGAs and SoC FPGAs
    Stratix® V FPGAs
    Cyclone® V FPGAs and SoC FPGAs