Article ID: 000085164 Content Type: Troubleshooting Last Reviewed: 11/29/2012

What is the "minimum pulse width timing specification" of the global reset signal for the UniPHY Controller?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

Global reset in the UniPHY Controller is connected to PLL areset port. Therefore PLL areset port minimum pulse width (tARESET) for your device will be minimum pulse width timing specification.
For example, tARESET for Stratix® IV and Stratix® V devices are 10ns.

Related Products

This article applies to 7 products

Stratix® IV E FPGA
Stratix® IV GT FPGA
Stratix® IV GX FPGA
Stratix® V E FPGA
Stratix® V GS FPGA
Stratix® V GT FPGA
Stratix® V GX FPGA