Article ID: 000086126 Content Type: Troubleshooting Last Reviewed: 02/07/2014

Timing Closure for Hard LPDDR2 Interfaces May Not be Robust in Cyclone V SoC Devices

Environment

  • Quartus® II Subscription Edition
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    Critical Issue

    Description

    This problem affects LPDDR2 products.

    Hard LPDDR2 interfaces targeting Cyclone V SoC devices may have difficulty achieving timing closure.

    Resolution

    There is no workaround for this issue.

    This issue is fixed in release 13.1.

    Related Products

    This article applies to 1 products

    Cyclone® V FPGAs and SoC FPGAs