While using the Intel® Quartus® Prime Pro Edition Software version, you may see the following error message using Intel Agilex® 7 FPGA EMIF IP and Intel® Stratix® 10 FPGA when your design is attempting to run Timing Analyzer on a design with no core logic. The Tcl timing script expects registers to be connected to amm_* interface and failed to analyze those paths.
Error(23035): Tcl error: ERROR: Collection does not exist with name. Specify the collection name returned by a Tcl command that supports "foreach_in_collection." Note a valid collection name can become invalid if the variable holding the collection goes out of scope, as well as a result of some built-in TCL commands, for example, 'string length.'
To work around this problem in the Intel® Quartus® Prime Pro Edition Software, implement one of the two options provided below:
• Connect amm_* signal to your design using Traffic Generator 2.0 (TG2) Toolkit for the Intel Agilex® 7 FPGA DDR4 IP and Intel® Stratix® 10 DDR4 or
• Include the following assignment in the .qsf file.
set_global_assignment -name VERILOG_MACRO "ALTERA_EMIF_ENABLE_ISSP=1"
This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Edition Software.