Article ID: 000087495 Content Type: Error Messages Last Reviewed: 04/18/2022

Why does the F-Tile Ethernet Intel® FPGA Hard IP design example that uses 10GE-1 with PTP variant fails to pass the “Support-Logic Generation” phase when using a custom system PLL frequency?

Environment

  • Intel® Quartus® Prime Pro Edition
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    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition Software v21.2, the F-Tile Ethernet Intel® FPGA Hard IP design example fails to pass the “Support Logic Generation” phase in the Intel Quartus Prime Software.

    The following error message occurs when using the 10GE-1 with PTP-enabled variant and a custom system phase-locked loop (PLL) frequency such as 903.125 MHz:

    “Error (21842): Solver failed to find a solution”

    Resolution

    To work around this problem in the Intel® Quartus® Prime Pro Edition Software v21.2, choose the default system PLL frequency of 805.664062 MHz when using the 10GE-1 with PTP variant.

     

    This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 22.1.

    Related Products

    This article applies to 1 products

    Intel Agilex® 7 FPGAs and SoC FPGAs I-Series