Article ID: 000091267 Content Type: Troubleshooting Last Reviewed: 06/15/2023

Why do I get an error related to bit range while using the Advanced SEU Detection Intel® FPGA IP for Intel Agilex® 7 FPGA?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Advanced SEU Detection Intel® FPGA IP
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    Description

    The total CRAM sector range for the Intel Agilex® 7 FPGAs is from 0-4159 (0X103F), while the maximum bit covered in Advanced SEU Detection Intel® FPGA IP is 4095 (0xFFF). The current Advanced SEU Detection Intel® FPGA IP bit range (12 bits) is insufficient to cover all the bit positions within the frame for the affected Intel Agilex® 7 FPGAs.

    As a result, an inaccurate report is shown (0x000-0x03F) when the SEU event happens within the bit range 4096-4159. When the error reporting value is between 0x000-0x03F, the bit range affected could be from 0-63 or 4096-4159. This problem also affects the Fault Injection Debugger Tool.

    However, SEU detection and correction are still working fine for the entire bit position.

     

     

    Resolution

    This problem has been fixed in the Intel® Quartus® Prime Pro Edition Software v23.1

    Related Products

    This article applies to 1 products

    Intel Agilex® 7 FPGAs and SoC FPGAs