Article ID: 000092752 Content Type: Errata Last Reviewed: 04/11/2023

Why do the Intel Agilex® 7 devices fail to reconfigure after the F-tile System PLL reference clock has a temporary loss?

Environment

  • Intel® Quartus® Prime Pro Edition
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    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 23.1 and earlier, if your F-tile System PLL reference clock experiences discontinuity or temporary loss condition, you might observe the Intel Agilex® 7 device fails to reconfigure.  

    Intel recommends you provide a stable reference clock throughout the design operation once your reference clock for the F-tile System PLL is available.

    If you cannot adhere to this, you must reconfigure the device.

     

    Resolution

    To work around this problem, you should try configuring your device again if your first reconfiguration fails.

    This problem will be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.

    Related Products

    This article applies to 1 products

    Intel Agilex® 7 FPGAs and SoC FPGAs F-Series