Intel® FPGA Design Examples

Learn in this overview how the Digital Blocks TFT LCD Controller reference design enables you to accelerate the design-in of TFT LCD panel displays in your system.

The state-based triggering flow allows you to define a custom triggering flow to organize triggering conditions. These examples show templates for common triggering flow scenarios.

The Intel drive-on-a-chip motor control reference design is an integrated drive system on a single Cyclone V SoC or Intel MAX 10. Learn more in this guide.

Intel offers a PCI Express (PCIe*) to External Memory reference design that demonstrates the operation of PCIe-based MegaCore function with a DDR2 or DDR3 SDRAM memory controller.

Single-Port Triple-Speed Ethernet On-Board PHY Chip datapath reference design provides a simple and quick way to implement your own Ethernet-based design in an Intel FPGA.

10-Gbps Ethernet Hardware Demonstration reference design provides a quick way to implement your 10-Gbps Ethernet (10GbE)-based design in an Intel FPGA.

Follow this guide to learn how the automotive digital radar reference design quickly develops and verifies hardware accelerators using our advanced development tools.

This design example shows you how to use the Cyclone® III RSU feature in AP mode.

Timing Analyzer Set Multicycle Path Command

SDC min and max delay description.

Timing analyzer UI description.

SDC create_generated_clocks