Intel® FPGA Package and Thermal Information
Package information includes the ordering code reference, package acronym, leadframe material, lead finish (plating), JEDEC® outline reference, lead coplanarity, weight, moisture sensitivity level, and other special information. The thermal resistance information includes device pin count, package name, and resistance values.
Intel® Stratix® Series |
Intel® Arria® Series |
Intel® Cyclone® Series |
Intel® MAX® Series |
HardCopy® Series |
Serial Configuration Devices |
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For other devices not listed in the table above, please see the devices packaging datasheet.
Search using package drawing search.
For other related packaging technical information, refer to the following literature.
Package and Thermal Application Notes and White Papers
Title |
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Application Notes |
AN752: Guidelines for Handling Intel® FPGA Wafer level chip scale package |
AN657: Thermal management and mechanical handling for Intel FPGA TCFCBGA devices |
AN659: Thermal management and mechanical handling for lidless flip chip ball-grid array |
AN 114: Designing with high-density BGA packages for Intel devices |
AN 71: Guidelines for handling J-Lead, QFP, BGA, FBGA, and lidless devices |
White Papers |
Challenges in manufacturing reliable lead-free and RoHS-compliant components |