DisplayPort IP Support Center

Welcome to the DisplayPort intellectual property (IP) core support center!

Here you will find information on how to plan, select, design, implement, and verify your DisplayPort IP cores. There are also guidelines on how to bring up your system and debug the DisplayPort links. This page is organized into categories that align with a DisplayPort system design flow from start to finish.

Enjoy your journey!

Get support resources for Intel® Stratix® 10, Intel Arria® 10, and Intel Cyclone® 10 devices from the pages below. For other devices, search from the following links: Documentation Archive, Training Courses, Videos and Webcasts, Design Examples, and Knowledge Base.

1. Device and IP Selection

Which Intel® FPGA Device Family Should I Use?

Link Rate Supported by Device Family

What is the DisplayPort Intel FPGA IP Core FPGA Resource Utilization?

The table below shows the resource information for Arria V and Cyclone V devices using M10K;

Intel Arria 10, Intel Stratix 10, and Stratix V devices using M20K.

The resources were obtained using the following parameter settings:

• Mode = simplex
• Maximum lane count = 4 lanes
• Maximum video input color depth = 8 bits per color (bpc)
• Pixel input mode = 1 pixel per clock

This section contains tables showing IP core variation size and performance examples.

The above table lists the resources and expected performance for selected variations.

The results were obtained using the Intel® Quartus® Prime Software v19.1 for the following devices:

• Intel Arria 10 (10AX115S2F45I1SG)
• Intel Cyclone 10 GX (10CX220YF780E5G)
• Intel Stratix 10 (1SG280HU1F50E2VGS1)
• Arria V (5AGXFB3H4F40C5)
• Cyclone V (5CGTFD9E5F35C7)
• Stratix V (5SGXEA7K2F40C2)

2. Design Flow and IP Integration

What is the DisplayPort-related information/documentation available?

Intel Stratix 10, Intel Arria 10, and Intel Cyclone 10 Devices

• DisplayPort Intel FPGA IP User Guide (HTML | PDF)

Intel Stratix 10 Devices

• Intel FPGA DisplayPort Design Example User Guide for Intel Stratix 10 Devices (HTML | PDF)

Intel Arria 10 Devices

• Intel FPGA DisplayPort Design Example User Guide for Intel Arria 10 Devices (HTML | PDF)

Intel Cyclone 10 Devices

• Intel FPGA DisplayPort Design Example User Guide for Intel Cyclone 10 Devices (HTML | PDF)

How do I generate the DisplayPort IP core?

To generate the DisplayPort IP core, follow these steps:

• Create an Intel Quartus Prime software project using the New Project Wizard available from the File menu.
• On the Tools menu, click IP Catalog.
• Under Installed IP, double-click Library > Interface Protocols > Audio &Video > DisplayPort Intel FPGA IP. The parameter editor appears.
• In the parameter editor, specify a top-level name for your custom IP variation. This name identifies the IP core variation files in your project. If prompted, also specify the targeted Intel FPGA family and output file HDL preference. Click OK.
• Specify parameters and options in the DisplayPort parameter editor: Optionally select preset parameter values. Presets specify all initial parameter values for specific applications (where provided). Specify parameters defining the IP core functionality, port configurations, and device-specific features. Specify options for processing the IP core files in other EDA tools.
• Click Generate to generate the IP core and supporting files, including simulation models.
• Click Close when file generation completes.
• Click Finish.
• If you generate the DisplayPort Intel FPGA IP core instance in an Intel Quartus Prime software project, you are prompted to add Intel Quartus Prime software IP File (.qip) and Intel Quartus Prime software Simulation IP File (.sip) to the current Intel Quartus Prime software project.

Similarly, the above steps can be found in the DisplayPort IP Core User Guide:

• Steps to generate DisplayPort IP Core in the Intel Quartus Prime software ›

What is supported in the Quartus generated DisplayPort design example?

The DisplayPort Intel FPGA IP core design examples demonstrate parallel loopback from DisplayPort RX instance to DisplayPort TX instance with or without a Pixel Clock Recovery (PCR) module. Below table represent design example options available for 10-series device.

Note: For Intel Stratix 10 Devices, HBR3 support is preliminary.

How do I generate the Quartus DisplayPort design example?

For 10-series device, use the DisplayPort Intel FPGA parameter editor in the Intel Quartus Prime Pro Edition software to generate the design example.

• Click Tools > IP Catalog, and select target device family.
• In the IP Catalog, locate and double-click DisplayPort Intel FPGA IP. The New IP Variation window appears.
• Specify a top-level name for your custom IP variation. The parameter editor saves the IP variation settings in a file named ip.
• You may select a specific FPGA device in the Device field, or keep the default Intel Quartus Prime software device selection.
• Click OK. The parameter editor appears.
• Configure the desired parameters for both TX and RX. Note: The DisplayPort design example generation flow supports only SST. Selecting the Support MST parameter prevents you from generating the example design.
• On the Design Example tab, select DisplayPort SST Parallel Loopback With PCR or DisplayPort SST Parallel Loopback Without PCR.
• Select Simulation to generate the testbench, and select Synthesis to generate the hardware design example. You must select at least one of these options to generate the design example files. If you select both, the generation time is longer.
• For Target Development Kit, select the available Intel FPGA development kit. If you select the development kit, then the target device (selected in step 4) changes to match the device on the development kit.
• Click Generate Example Design.

Similarly, the links below provides step-by-step instruction to generate DisplayPort design example from the Intel Quartus Prime software:

• Intel Stratix 10 FPGA ›
• Intel Arria 10 FPGA ›
• Intel Cyclone 10 FPGA ›

How do I compile and test my design?

For 10-series devices, the steps to compile and test your DisplayPort design can be found in the following DisplayPort Design Example User Guides, under section "Compiling and Testing the Design":

• Intel Stratix 10 FPGA ›
• Intel Arria 10 FPGA ›
• Intel Cyclone 10 FPGA ›

How can I perform DisplayPort functional simulation?

For 10-series device, below are the steps to generate DisplayPort functional simulation:

• Enable the simulation option in the DisplayPort Parameter Editor and generate DisplayPort design example.
• Perform the simulation ›
• Understanding the testbench ›

Where do I find information on the Clock Recovery Core?

The 10-series DisplayPort design example uses Pixel Clock Recovery IP. The Clock Recovery Core information can be found in the link below:

• Intel® DisplayPort IP Core User Guide ›

Where do I find information on the DisplayPort Link Training flow?

Before the source device can send video data to sink device, a Link Training process has to be completed between source-sink. The information about the Link Training process can be found at the following link:

• Intel DisplayPort IP Core User Guide ›

Where do I find information on the DisplayPort API reference and DPCD information?

The following links will direct you to the DisplayPort application programming interface (API) reference and DPCD information:

• Source-supported DPCD locations ›
• Sink-supported DPCD locations ›
• Link to DisplayPort API reference information ›

3. Board Design and Power Management

Pin Connection Guidelines

Intel Stratix 10 Devices

• Intel Stratix 10 GX, MX, TX and SX Device Family Pin Connection Guidelines ›

Intel Arria 10 Devices

• Intel Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines ›

Intel Cyclone 10 Devices

• Intel Cyclone 10 GX Device Family Pin Connection Guidelines ›

Schematic Review

Intel Stratix 10 Devices

• Intel Stratix 10 GX, MX, and SX Schematic Review Worksheet ›
• Intel Stratix 10 GX FPGA Development Kit User Guides and Schematics ›
• Intel Stratix 10 SX SoC Development Kit User Guides and Schematics ›

Intel Arria 10 Devices

• Intel Arria 10 GX, GT, and SX Schematic Review Worksheet ›
• Intel Arria 10 GX FPGA Development Kit User Guides and Schematics ›
• Intel Arria 10 SoC Development Kit User Guides and Schematics ›

Intel Cyclone 10 Devices

• Intel Cyclone 10 GX Schematic Review Worksheet ›
• Intel Cyclone 10 GX FPGA Development Kit User Guides and Schematics ›

Board Design Guidelines

• Board Design Guidelines Solutions ›
• Board Layout Test ›
• AN 114: Board Design Guidelines for Intel® Programmable Device Packages ›
• AN 766: Intel Stratix 10 Devices, High-Speed Signal Interface Layout Design Guideline ›
• AN 613: PCB Stackup Design Considerations for Intel FPGAs ›
• AN745: Design Guideline for Intel FPGA DisplayPort Interface (HTML | PDF)
• FMC DisplayPort Daughter Card Revision 8 Schematics ›
• FMC DisplayPort Daughter Card Revision 11 Schematics ›
• HSMC DisplayPort 1.2 Daughter Card Schematics ›

Disclaimer: The Intel Arria 10 and Intel Stratix 10 Development Kit on-board DisplayPort TX board design implementation is NOT recommended as it does not allow PMA + PCS bonding. Users are advised to refer tp the Bitec design implementation.

Power Management

• Early Power Estimator (EPE) and Power Analyzer ›
• AN 750: Using the Intel FPGA PDN Tool to Optimize Your Power Delivery Network Design ›
• Device-Specific Power Deliver Network (PDN) Tool 2.0 User Guide ›

Thermal Power Management

Intel Stratix 10 Devices

• AN 787: Intel Stratix 10 Thermal Modeling and Management (HTML | PDF)

Power Sequencing

Intel Stratix 10, Intel Cyclone 10, and Intel Arria 10 Devices

• AN 692: Power Sequencing Considerations for Intel Cyclone 10 GX, Intel Arria 10, and Intel Stratix 10 Devices (HTML | PDF)

My design require Bitec FMC daughter card. How do I select them?

The following table provides a quick guideline in selecting Bitec FMC daughtercard revision

Any requirement to use single or dual lanes transceiver channel with Bitec FMC daughter card for 10-series devices?

Yes. For DisplayPort design that uses/referred to in an early version of Bitec FMC daughtercard (revision 9 and earlier), the pin assignment in the following link has to be followed at TX and RX due to the lane reversal and polarity inversion at the channel.

How do I create a DisplayPort TX-only or RX-only design?

A general guideline to create a DisplayPort TX-only or RX-only design can be found in the Intel DisplayPort Design Example User Guide. Alternatively, a more detailed explanation specific to the DisplayPort TX-only design can be referred to in the AN 883: Intel Arria 10 DisplayPort TX-only Design User Guide.

4. Design Examples and Reference Designs

Intel Arria 10 Devices

• AN 793: Intel Arria 10 DisplayPort 4Kp60 with Video and Image Processing Pipeline Retransmit Reference Design (HTML | PDF)
• Intel Arria 10 DisplayPort TX-only Design User Guide (HTML | PDF)
• Intel Arria 10 DisplayPort Design Example using On-board Connector (TX-Only) ›
• DisplayPort UHD Scaler and Mixer Design Example User Guide ›

5. Debug

How do I debug my DisplayPort design?

There are several debug options available in our DisplayPort design example that can be integrated into the user design:

• Observing the Development Kit On-board User LED ›
• Observing the Main Stream Attributes Information and Auxiliary Channel Traffic ›
• Intel DisplayPort Bandwidth & PCR Calculator

Intellectual Property (IP) Core Release Notes

• DisplayPort IP Core Release Notes (HTML | PDF)

Knowledge Base Solution

• Search the Knowledge Base (Intel Cyclone 10 Devices) ›
• Search the Knowledge Base (Intel Arria 10 Devices) ›
• Search the Knowledge Base (Intel Stratix 10 Devices) ›