Transceiver PHY IP Support Center

Welcome to the Transceiver PHY IP support center!

Here you will find information on how to select, design, and implement transceiver links. There are also guidelines on how to bring up your system and debug the transceiver links. This page is organized into categories that align with a high-speed transceiver system design flow from start to finish.

Enjoy your journey!

Get support resources for Intel® Agilex™, Intel® Stratix® 10, Intel® Arria® 10, and Intel® Cyclone® 10 devices from the pages below. For other devices, search from the following links: Training Course Videos, Webcasts Design Examples, and Knowledge Base.

1. Device and IP Selection

Which Intel® FPGA Device Family Should I Use?

Table 1 - Device Variant and Feature Support

Device

Intel Cyclone 10

Intel Arria 10

Intel Stratix 10

 Intel Agilex

Device Variant

GX

SX(3)

GX(3)

GT(4)

GX/SX L-Tile

GX/SX H-Tile

MX/TX E-Tile

AGF E-Tile

Maximum Data Rate
(Chip-to-Chip)(1)(7)


GX Channels

12.5 Gbps

17.4 Gbps

17.4 Gbps

17.4 Gbps

17.4 Gbps

N/A

N/A

GXT Channels

N/A

N/A

25.8 Gbps

26.6 Gbps

28.3 Gbps

28.3 Gbps

N/A

GXE Channels

N/A

N/A
N/A
N/A

N/A

28.9 Gbps (NRZ)

57.8 Gbps (PAM4)

28.9 Gbps (NRZ)

57.8 Gbps (PAM4)

Maximum Data Rate
(Backplane)(8)

GX Channels

6.6Gbps

12.5 Gbps

12.5 Gbps

12.5 Gbps

28.3 Gbps 28.3 Gbps N/A

GXT Channels

N/A

N/A


GXE Channels

N/A

N/A

N/A

N/A

N/A

28.9 Gbps (NRZ)

57.8 Gbps (PAM4)

28.9 Gbps (NRZ)

57.8 Gbps (PAM4)

Maximum Channels per device

GX Channels

12

96

72

96

96 N/A

N/A 

GXT Channels

N/A

N/A

6

32

64

24

N/A

GXE Channels

N/A

N/A

N/A

N/A

N/A 120

24 (and 32 P-Tile)

Hard IP One PCIe Gen2 x4 per device. PCIe* Gen3 x8 up to 4 per device PCIe Gen3 x16 up to 4 per device PCIe Gen3 x16 up to 4 per device 50/100 Gbps Ethernet MACup to 4 per device PCIe Gen3 x16 up to 4 per device SR-IOV (four PF/2K VF) (6) 10G/25G/100G Ethernet with optional 1588 capability + RS-FEC (528, 514)/RS-FEC (544, 514) 10G/25G/100G Ethernet with optional 1588 capability + RS-FEC (528, 514)/RS-FEC (544, 514)
SR-IOV support is not available.
  1. The values shown in the table above are for standard power modes. In reduced power mode, the maximum data rate for Intel Arria® 10 GX device channels (chip-to-chip) is 11.3 Gbps. As the GT transceiver channels are designed for peak performance, they do not have a reduced power mode of operation. To operate GX transceiver channels at designated data rates in standard and reduced power modes, apply the corresponding core and periphery power supplies. For more details, refer to the Intel Arria 10 Device Datasheet.
  2. Intel Arria 10 and Intel Stratix 10 device transceivers can support data rates below 1.0 Gbps through over sampling.
  3. For SX and GX device variants, the maximum transceiver data rates are specified for the fastest (–1) transceiver speed grade. Refer to the Device Datasheet for lower speed grade specifications.
  4. For GT device variants, the maximum transceiver data rates are specified for (-1) transceiver speed grade. Refer to the Device Datasheet for the lower speed grade specifications.
  5. Intel Stratix 10 device transceivers have both GX and GXT types of transceiver channels. For details, refer to the Intel Stratix 10 L-/H-Tile Transceiver PHY User Guide.
  6. SR-IOV stands for Single-Root Input Output Virtualization.
  7. Intel Arria 10 and Intel Stratix 10 device transceivers can support data rates below 1.0 Gbps through over sampling.
  8. Backplane applications refer to the ones that require advanced equalization, such as decision feedback equalization (DFE) enabled to compensate for channel loss.

Intel FPGA Device Datasheets

Additional Resources

Refer to the Overview chapter of the following user guides:

Intel Agilex Devices

Intel Stratix 10 Devices

Intel Cyclone 10 Devices

Intel Arria 10 Devices

2. Design Flow and IP Integration

Where Can I Find Information on Transceiver Usage?

Use the E-Tile Channel Placement Tool in conjunction with the Intel Stratix 10 Device Family Pin Connection Guidelines, to swiftly plan protocol placements in the E-Tile prior to reading comprehensive documentation and implementing designs in the Intel® Quartus® Prime software. The Excel-based E-Tile Channel Placement Tool is supplemented with instruction, legend, revision, and protocols tabs.

What Design Recommendations Should I Consider?

Intel Agilex Devices

Intel Stratix 10 Devices

Intel Cyclone 10 Devices

Intel Arria 10 Devices

Where Can I Find Information on Transceiver PHY IP Integration?

Intel Agilex Devices

Intel Stratix 10 Devices

Intel Cyclone 10 Devices

Intel Arria 10 Devices

Where Can I Find Information on the Transceiver PHY IP Register Mapping?

Intel Stratix 10 Devices

Intel Cyclone 10 Devices

Intel Arria 10 Devices

Analog Settings Guidelines

Intel Stratix 10 Devices

Intel Cyclone 10 and Intel Arria 10 Devices

Additional Resources

 

3. Board Design and Power Management

Board Design Guidelines

Pin Connection Guidelines

Intel Agilex Devices

Intel Stratix 10 Devices

Intel Cyclone 10 Devices

Intel Arria 10 Devices

Schematic Review

Intel Agilex Devices

Intel Stratix 10 Devices

Intel Cyclone 10 Devices

Intel Arria 10 Devices

Power Management

Simulation Models & Tools

Intel ® Advanced Link Analyzer ›

The Intel® Advanced Link Analyzer is a state-of-the art jitter/noise eye link analysis tool that allows you to quickly and easily evaluate high-speed serial link performance. It is an ideal pre-design tool to help you understand how Intel FPGA solutions can fit your system requirements. It is also an effective tool for post-design support to assist in debug and validation.

Models

Development Kit User Guides

Intel Agilex Devices

Intel Stratix 10 Devices

Intel Arria 10 Devices

6. Training Courses and Videos

Recommended Training Courses

Title

Type

Description 

Building Interfaces with Intel Arria 10 High-Speed Transceivers

Instructor-Led

Learn the architecture of Intel Arria 10 and Intel Cyclone 10 FPGA transceivers and then the flow for incorporating them into an FPGA design.

Transceiver Basics for 20 nm and 28 nm Devices

Online

Learn the basic building blocks that are found in 20 and 28 nm FPGA transceivers used to support a range of high-speed protocols.

Intel Stratix 10 Transceiver Basics

Online

Learn the basic building blocks that are found in Intel Stratix 10 FPGA transceivers used to support a range of high-speed protocols.

Transceiver Toolkit for Intel Arria 10 Devices

Online

Learn how to debug and dynamically fine tune the analog settings of your Intel Arria 10 and Intel Cyclone 10 FPGA transceivers.

Advanced Signal Conditioning for Intel Arria 10 FPGA Transceivers

Online

Learn the analog capabilities of Intel Arria 10 FPGA transceivers and how to use them to improve link performance.

Building a Generation 10 Transceiver PHY Layer

Online

Learn how to build a custom transceiver implementation using the Intel Arria 10 and Intel Cyclone 10 FPGA transceiver IP blocks.

Building an Intel Stratix 10 FPGA Transceiver PHY Layer

Online 

Learn how to define the three resources that make up an Intel Stratix 10 FPGA transceiver PHY layer solution, namely, the transceiver PHY, the transceiver PLL and the transceiver reset controller.

Generation 10 Transceiver Clocking

Online

Learn the clocking resources that are found in Intel Arria 10 and Intel Cyclone 10 FPGA transceiver blocks.

Other Training Courses

Recommended Videos

Title

Description

How to Dynamically Reconfigure PMA Analog Parameters for Intel Cyclone 10 GX

Learn the implementation of Intel Cyclone 10 GX FPGA Native PHY PMA analog parameters using direct reconfiguration flow.

How to Perform the Intel Cyclone 10 GX Dynamic Reconfiguration with fPLL Switching and Channel Reconfiguration Using Direct Write Method

Learn how to perform the transceiver dynamic reconfiguration functional simulation with Intel Cyclone 10 GX FPGA fractional phase-locked loop (PLL) switching and channel reconfiguration using the direct write method.

How to Perform Intel Cyclone 10 GX Native PHY ATX PLL Switching and Channel Reconfiguration

Learn how to perform the functional simulation with Intel Cyclone 10 GX FPGA Native PHY ATX PLL switching, channel reconfiguration with embedded streamer, and channel recalibration.

How to Switch the CDR refclk Selection Using Embedded Streamer and Reconfiguration Profiles in Intel Arria 10 Native PHY

Learn how to perform dynamic reconfiguration to switch the clock data recovery (CDR) refclks with embedded streamer and multiple reconfiguration profiles in the Intel Arria 10 device.

How to Configure Two FPGAs that is Externally Connected through SMA Cables Using Transceiver Toolkit

Learn how to configure two device under test (DUTs), launch transceiver (XCVR) toolkits, perform chip-to-chip interface, and find the right analog settings.

How to Perform Dynamic Reconfiguration to Switch TX PLLs for the Intel Arria 10 Transceiver Using Embedded Streamer

Learn how to perform dynamic reconfiguration to switch transmitter (TX) PLLs for the Intel Arria 10 FPGA transceiver using embedded streamer.

Other Videos

Title

Description

Intel Arria 10 Device Configuration of a Simplex Transceiver

Watch this video to learn how to place an Intel Arria 10 device simplex transceiver with dynamic reconfiguration in the same physical transceiver channel.

Dynamic Reconfiguration of an Intel Arria 10 Device Transceiver

Watch this video to learn how to perform data rate changes using transmit (TX) phase-locked loop (PLL) switching and the embedded streamer in Intel Arria 10 devices.

How to Use the Transceiver Toolkit Part 1

Watch this four-part video to learn how to use the Transceiver Toolkit application, demonstrated on an Intel Arria 10 FPGA Development Kit. This video explains how to get the optimal physical medium attachment (PMA) settings for the transceiver.

How to Use the Transceiver Toolkit Part 2

Watch this four-part video to learn how to use the Transceiver Toolkit application, demonstrated on an Intel Arria 10 FPGA Development Kit. This video explains how to get the optimal PMA settings for the transceiver.

How to Use the Transceiver Toolkit Part 3

Watch this four-part video to learn how to use the Transceiver Toolkit application, demonstrated on an Intel Arria 10 FPGA Development Kit. This video explains how to get the optimal PMA settings for the transceiver.

How to Use the Transceiver Toolkit Part 4

Watch this four-part video to learn how to use the Transceiver Toolkit application, demonstrated on an Intel Arria 10 FPGA Development Kit. This video explains how to get the optimal PMA settings for the transceiver.

Intel Arria 10 Transceivers: Pre-Emphasis Basics

Learn the basics of the Intel Arria 10 Transceiver Pre-Emphasis feature. Compare simulated waveform versus silicon measurements.

Performing Dynamic Reconfiguration for the Intel Arria 10 Device Transceiver

Watch this video to learn how to perform data rate changes using TX PLL switching with the embedded streamer in Intel Arria 10 devices.

Reconfigure Intel Arria 10 Device Transceivers Using Embedded Streamer

Watch this video to learn how to perform dynamic reconfiguration with the Intel Arria 10 device transceiver Standard PCS using the embedded streamer.

Use the IBIS-AMI Model to Estimate Signal Integrity of Intel Arria 10 Device Transceiver

Watch this video to learn how to perform a signal integrity simulation with the Intel Arria 10 device transceiver IBIS-AMI model in the Intel® Advanced Link Analyzer. Additionally, this video covers eye diagram reporting.

7. Debug

Tools

Intel Stratix 10 Device E-Tile Transceiver Debug Tool

The debug tool consists of two sub-tools

  1. Status tool enables you to read and reset PMA parameters and log it in a file. It also enables you to perform adaptation flow (Internal/external loopback, initial adaptation), read and reset bit errors.
  2. Tuning tool enables you to tune the transceiver with base line PMA parameter configurations for 10Gbps/28Gbps/56Gbps and with custom parameters it enables you to sweep PMA parameters and log it in a file. Use this tool to analyze the health of the transceiver channels in your Intel Stratix 10 Device E-Tile.

Intel Stratix 10 Device L-Tile/H-Tile Transceiver PHY Debug Tool

This debug tool consists of four sub-tools:

  1. Voltage tool enables you to measure the voltage at the receiver data sampling node and transmitter node
  2. Channel Status tool enables you to check the status locked to data of receiver clock data recovery (CDR), calibration status, loopback status and PRBS generator/checker status
  3. Adaptation status tool enables you to cross verify the configured adaptation registered bits against the golden bit settings -Golden bits are the recommended bit settings for a given register
  4. Eye debug tool enables you to measure the eye height and/or eye width

Use this tool to analyze the health of the transceiver channels in your Intel Stratix 10 Device L-Tile/H-Tile

Intel Arria 10 Device Transceiver PHY - Fault Tree Analyzer

This interactive fault tree analyzer provides guidelines for troubleshooting issues you may encounter while using Intel Arria 10 Device Transceiver PHY. The analyzer consists of three sections:

  1. Native PHY Debug
  2. Link Tuning Debug
  3. Dynamic Reconfiguration Debug

Use this fault tree analyzer to help you resolve Transceiver PHY issues and bring up your design as efficiently as possible. Use it along with the Intel Arria 10 Device Transceiver PHY Debug Tool

Intel Arria 10 Device Transceiver PHY Debug Tool

This debug tool consists of the same four sub-tools as the Intel Stratix 10 version:

  1. Voltage tool enables you to measure the voltage at the receiver data sampling node and transmitter node
  2. Channel Status tool enables you to check the status locked to data of receiver clock data recovery (CDR), calibration status, loopback status and PRBS generator/checker status
  3. Adaptation status tool enables you to cross verify the configured adaptation registered bits against the golden bit settings -Golden bits are the recommended bit settings for a given register
  4. Eye debug tool enables you to measure the eye height and/or eye width

Use this tool to analyze the health of the transceiver channels in your Intel Arria 10 Device