CPRI Intel® FPGA IP User Guide

ID 683595
Date 5/17/2024
Public
Document Table of Contents

2.5.7.1. System PLL Connections for the Agilex® 7 F-tile Variations

Figure 8. System PLL Connection to CPRI IP for Static Rate and Rate Switch Configurations that involves only one type of line bit rate encoding
Figure 9. System PLL Connection to CPRI IP for Rate Switch Configurations that involves both types of line bit rate encoding