Turbo Intel® FPGA IP User Guide

Download PDF
ID 683734
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the Turbo Intel® FPGA IP 2. Getting Started with the Turbo Intel® FPGA IP 3. Parameter Settings 4. Turbo Intel® FPGA IP Functional Description A. Turbo IP User Guide Document Archives 5. Document Revision History for Turbo Intel® FPGA IP User Guide
1. About the Turbo Intel® FPGA IP x
1.1. Turbo Intel® FPGA IP Features 1.2. Turbo Intel® FPGA IP Device Family Support 1.3. Turbo IP Performance and Resource Utilization 1.4. Turbo Code Licensing Disclaimer 1.5. Release Information
2. Getting Started with the Turbo Intel® FPGA IP x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. IP Catalog and Parameter Editor 2.3. Specifying the IP Core Parameters and Options 2.4. Simulating Intel® FPGA IP Cores 2.5. Simulating the IP with the RTL Simulator 2.6. Simulating the Turbo IP with the C-Model 2.7. Simulating the Turbo IP with MATLAB
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode 2.1.2. Turbo IP Timeout Behavior
2.3. Specifying the IP Core Parameters and Options x
2.3.1. IP Core Generation Output ( Quartus® Prime Pro Edition)
4. Turbo Intel® FPGA IP Functional Description x
4.1. Turbo Encoder 4.2. Turbo Decoder 4.3. 4.4. Turbo Throughput
4.1. Turbo Encoder x
4.1.1. Turbo Encoder Data Format 4.1.2. Turbo Encoder Latency Calculation
4.2. Turbo Decoder x
4.2.1. Turbo Decoder Data Format 4.2.2. CRC24A or CRC24B Early Termination 4.2.3. Decoder Latency Calculation 4.2.4. Error Correction Performance for the Turbo Decoder
1. About the Turbo Intel® FPGA IP
2. Getting Started with the Turbo Intel® FPGA IP
3. Parameter Settings
4. Turbo Intel® FPGA IP Functional Description
A. Turbo IP User Guide Document Archives
5. Document Revision History for Turbo Intel® FPGA IP User Guide

1.5. Release Information

Intel® FPGA IP versions match the Quartus® Prime Design Suite software versions until v19.1. Starting in Quartus® Prime Design Suite software version 19.2, Intel® FPGA IP has a new versioning scheme.

The Intel® FPGA IP version (X.Y.Z) number can change with each Quartus® Prime software version. A change in:

  • X indicates a major revision of the IP. If you update the Quartus® Prime software, you must regenerate the IP.
  • Y indicates the IP includes new features. Regenerate your IP to include these new features.
  • Z indicates the IP includes minor changes. Regenerate your IP to include these changes.
Table 5.  Turbo Intel® FPGA IP Release Information
Item Description
IP Version 22.3.3
Release Date August 2023
Ordering Code IP-TURBO (IPR-TURBO)
Related Information
Level Two Title