AN 705: Scalable 10G Ethernet MAC using 1G/10G PHY

ID 683066
Date 5/13/2016
Public
Document Table of Contents

1.10.7. Packet Classifier Interface Signals

Table 16.  Packet Classifier Interface Signals
Signal Direction Width Description
tx_egress_timestamp_request_in_valid[] input [NUM_CHANNELS] Assert this signal when timestamp is required for the particular frame. This signal must be aligned to the start of an incoming packet.
tx_egress_timestamp_request_in_fingerprint[][] input [NUM_CHANNELS][TSTAMP_FP_WIDTH] A width-configurable fingerprint that correlates timestamps for incoming packets.
clock_operation_mode_mode[][] input [NUM_CHANNELS][2] Determines the clock mode.
  • 00: Ordinary clock
  • 01: Boundary clock
  • 10: End to end transparent clock
  • 11: Peer to peer transparent clock
pkt_with_crc_mode[] input [NUM_CHANNELS] Indicates whether or not a packet contains CRC.
  • 0: Packet contains CRC
  • 1: Packet does not contain CRC
tx_ingress_timestamp_valid[] input [NUM_CHANNELS] Indicates the update for residence time.
  • 0: Prevents update for residence time
  • 1: Allows update for residence time based on decoded results

When this signal is deasserted, tx_etstamp_ins_ctrl_out_residence_ti me_update also gets deasserted.

tx_ingress_timestamp_96b_data[][] input [NUM_CHANNELS][96] 96-bit format of ingress timestamp that holds data so that the output can align with the start of an incoming packet.
tx_ingress_timestamp_64b_data[][] input [NUM_CHANNELS][64] 64-bit format of ingress timestamp that holds data so that the output can align with the start of an incoming packet.
tx_ingress_timestamp_format[] input [NUM_CHANNELS] Format of the timestamp to be used for calculating residence time. This signal must be aligned to the start of an incoming packet. A value of 0 indicates 96 bit timestamp format while 1 indicates 64 bit timestamp format.