25G Ethernet Intel® FPGA IP Release Notes

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ID 683067
Date 8/01/2023
Public
Document Table of Contents
Document Table of Contents x
1. 25G Ethernet Intel® FPGA IP Release Notes (Intel Stratix 10 Devices) 2. 25G Ethernet Intel® FPGA IP Release Notes (Intel Arria 10 Devices)
1. 25G Ethernet Intel® FPGA IP Release Notes (Intel Stratix 10 Devices) x
1.1. 25G Intel® FPGA IP Ethernet v20.1.0 1.2. 25G Ethernet Intel® FPGA IP v20.0.0 1.3. 25G Ethernet Intel® FPGA IP v19.5.0 1.4. 25G Ethernet Intel® FPGA IP v19.4.1 1.5. 25G Ethernet Intel® FPGA IP v19.4.0 1.6. 25G Ethernet Intel® FPGA IP v19.3.0 1.7. 25G Ethernet Intel® FPGA IP v19.2.0 1.8. 25G Ethernet Intel® FPGA IP v19.1 1.9. 25G Ethernet Intel® FPGA IP v18.1 1.10. 25G Ethernet Intel® FPGA IP v18.0 1.11. 25G Ethernet Intel® Stratix® 10 FPGA IP User Guide Archives 1.12. 25G Ethernet Intel® Stratix® 10 FPGA IP Design Example User Guide Archives
2. 25G Ethernet Intel® FPGA IP Release Notes (Intel Arria 10 Devices) x
2.1. 25G Ethernet Intel® FPGA IP v19.4.1 2.2. 25G Ethernet Intel® FPGA IP v19.4.0 2.3. 25G Ethernet Intel® FPGA IP v19.1 2.4. 25G Ethernet IP Core v17.0 2.5. 25G Ethernet IP Core v16.1 2.6. 25G Ethernet Intel® Arria® 10 FPGA IP User Guide Archive 2.7. 25G Ethernet Intel® Arria® 10 FPGA IP Design Example User Guide Archives
1. 25G Ethernet Intel® FPGA IP Release Notes (Intel Stratix 10 Devices)
2. 25G Ethernet Intel® FPGA IP Release Notes (Intel Arria 10 Devices)

1.4. 25G Ethernet Intel® FPGA IP v19.4.1

Table 4.  v19.4.1 2020.12.14
Intel® Quartus® Prime Version Description Impact
20.4
Length checking update on VLAN frames:
  • In previous versions of 25G Ethernet Intel® FPGA IP, oversized frame error is asserted when the following conditions are met:
    1. VLAN
      1. VLAN detection is enabled.
      2. The IP transmits/receives frames with length amounting to the maximum TX/RX frame length plus 1 to 4 octets.
    2. SVLAN
      1. SVLAN detection is enabled.
      2. The IP transmits/receives frames with length amounting to the maximum TX/RX frame length plus 1 to 8 octets.
  • In this version, the IP is updated to correct this behavior.
 —
Updated the Avalon® memory-mapped interface access to the status_* interface to prevent Avalon® memory-mapped timeout during reads to non-existent addresses:
  • In previous versions of 25G Ethernet Intel® FPGA IP, Avalon® memory-mapped interface reads to non-existent addresses on the status_* interface would assert status_waitrequest until the Avalon® memory-mapped master’s request times out. The issue has now been fixed to not hold waitrequest when a non-existent address is accessed.
—
RS-FEC enabled variants now support 100% throughput. —
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