AN 851: Incremental Block-Based Compilation Tutorial: for Intel® Arria® 10 FPGA Development Board

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ID 683079
Date 7/15/2019
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Document Table of Contents x
1. AN 851: Incremental Block-Based Compilation Tutorial for Intel® Arria® 10 FPGA Development Board
1. AN 851: Incremental Block-Based Compilation Tutorial for Intel® Arria® 10 FPGA Development Board x
1.1. Tutorial Design Overview 1.2. Downloading Tutorial Design Files 1.3. Incremental Block-Based Compilation Tutorial 1.4. Incremental Block-Based Compilation Tutorial Revision History
1.3. Incremental Block-Based Compilation Tutorial x
1.3.1. Step 1: Compile the Flat Design 1.3.2. Step 2: Identify Timing-Critical Design Blocks 1.3.3. Step 3: Create Design Partitions 1.3.4. Step 4: Analyze Timing of the Partitioned Design 1.3.5. Step 5: Preserve Timing-Closed Partitions 1.3.6. Step 6: Optimize Timing-Critical Design Blocks 1.3.7. Step 7: Verify Preservation and Optimized Results 1.3.8. (Optional) Step 8: Device Programming 1.3.9. (Optional) Step 9: Verify Results in Hardware
1. AN 851: Incremental Block-Based Compilation Tutorial for Intel® Arria® 10 FPGA Development Board

1.2. Downloading Tutorial Design Files

Follow these steps to use the design example files with this tutorial:
  1. Download and extract the tutorial design files at:
    https://www.intel.com/content/dam/www/programmable/us/en/others/literature/an/a10_pcie_devkit_ibbc.zip
  2. View the extracted tutorial design file directory structure. The completed directory contains the final versions of all the files for the tutorial. You can use the files in the completed directory for comparison to confirm successful completion of the tutorial steps. The scripts folder contains the original files.
Figure 2. Tutorial Directory Structure

The tutorial directory includes the following files:

Table 1.  Tutorial Directory Files
File Name Description
top.sv

Top-level file that instantiates the iopll, big_partition1_top, blinking_led_2s, blinking_led_4s, blinking_led_8s, and blinking_led_16s instances.

The file also includes logic to drive LED[4:7] as a single, shifting bit.
top.qpf Intel® Quartus® Prime project file that stores project name and revisions.
top.qsf Intel® Quartus® Prime settings file containing the project assignments and settings.
big_partition1_top.v Design file that instantiates 20 instances of an OpenCores* design.
blinking_led_2s.sv Design file that includes logic to drive LED[0] every two seconds.
blinking_led_4s.sv Design file that includes logic to drive LED[1] every four seconds.
blinking_led_8s.sv Design file that includes logic to drive LED[2] every eight seconds.
blinking_led_16s.sv Design file that includes logic to drive LED[3] every 16 seconds.
blinking_led.sdc A Synopsys Design Constraints file that creates the 50 MHz clock.
iopll.ip The IOPLL Intel® FPGA IP instantiated in top. The IP uses 50 MHz as the reference clock frequency, and generates 100 MHz and 550 MHz clocks.
tx_dcfifo.ip The FIFO Intel® FPGA IP instantiated in blinking_led_2s, blinking_led_4s, blinking_led_8s, and blinking_led_16s instances. This is a dual clock FIFO with a write clock of 550 MHz and read clock of 100 MHz.
compile.tcl A bash script that compiles the tutorial design at the command line.
partitions.tcl A tcl script that includes the assignments to create the partitions that the tutorial describes. Running the script writes the assignments to the Intel® Quartus® Prime Settings File (.qsf).
preserve.tcl A tcl script that includes the assignments to preserve the partitions that the tutorial describes. Running the script writes the assignments to the .qsf.
report_timing.tcl A tcl script that includes Intel® Quartus® Prime Timing Analyzer commands that generate summary of paths reports with least positive or worst slack in each partition, along with commands to report timing for two specific nodes in the three partitions that meet timing requirements.
  • To restore all of the tutorial files to their original state, run scripts/restore.tcl from the a10_pcie_devkit_ibbc/tutorial directory.

  • To compile the tutorial design from command line, run compile.tcl from the a10_pcie_devkit_ibbc/tutorial directory.

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