High-speed Reed-Solomon IP Core User Guide

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ID 683120
Date 11/06/2017
Public
Document Table of Contents
Document Table of Contents x
1. About the High-speed Reed-Solomon IP Core 2. High-speed Reed-Solomon IP Core Getting Started 3. High-speed Reed-Solomon IP Core Functional Description 4. High-speed Reed-Solomon IP Core User Guide Document Revision History A. High-Speed Reed-Solomon IP Core Document Archive
1. About the High-speed Reed-Solomon IP Core x
1.1. Reed-Solomon II versus High-Speed Reed Solomon Intel® FPGA IP 1.2. High-speed Reed-Solomon IP Core Features 1.3. High-Speed Reed-Solomon IP Device Family Support 1.4. DSP IP Core Verification 1.5. High-speed Reed-Solomon IP Core Release Information 1.6. High-speed Reed-Solomon IP Core Performance and Resource Utilization
2. High-speed Reed-Solomon IP Core Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. IP Catalog and Parameter Editor 2.3. Generating IP Cores ( Intel® Quartus® Prime Pro Edition) 2.4. Simulating Intel® FPGA IP Cores
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode 2.1.2. High-speed Reed-Solomon IP Core Intel® FPGA IP Evaluation Mode Timeout Behavior
2.3. Generating IP Cores ( Intel® Quartus® Prime Pro Edition) x
2.3.1. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition)
3. High-speed Reed-Solomon IP Core Functional Description x
3.1. High-Speed Reed-Solomon Architecture 3.2. High-Speed Reed-Solomon IP Core Parameters 3.3. High-speed Reed-Solomon IP Core Interfaces and Signals
3.1. High-Speed Reed-Solomon Architecture x
3.1.1. High-Speed Reed-Solomon Encoder 3.1.2. High-Speed Reed-Solomon Decoder
3.3. High-speed Reed-Solomon IP Core Interfaces and Signals x
3.3.1. High-speed Reed-Solomon IP Core Signals
1. About the High-speed Reed-Solomon IP Core
2. High-speed Reed-Solomon IP Core Getting Started
3. High-speed Reed-Solomon IP Core Functional Description
4. High-speed Reed-Solomon IP Core User Guide Document Revision History
A. High-Speed Reed-Solomon IP Core Document Archive

3.2. High-Speed Reed-Solomon IP Core Parameters

Table 11.  Parameters
Parameter Legal Values Default Value Description
Reed-Solomon Core Fractuarable 100G Ethernet or custom Custom -
Reed-Solomon module Encoder or Decoder Decoder An encoder or a decoder.
Custom IP Core
Number of channels 1 to 10 1 Decoder only.
Number of bits per symbol 3 to 12 8 The number of bits per symbol (M).
Number of symbols per codeword 1 to 2M – 1 255 The total number of symbols per codeword (N).
Number of data symbols per codeword 2 to N– 2 239 The number of data symbols per codeword (K = N - R). Where R is the number of check symbols.
Field polynomial Any valid polynomial 285 The primitive polynomial defining the Galois field. The parameter editor allows you to select only legal values. If you cannot find your intended field polynomial, contact Intel MySupport.
Parallelism P < N/2 3 The number of parallel inputs and outputs. The last output fills up with zeros.
Bypass Mode No or yes No Turn on to produce the received codeword without error correction but with only error detection. A message is output after few clock cycles.
Fractuarable IP core Parameters
100G Ethernet On On A single 100G channels with parallelism 32.
2 x 50G Ethernet On or off On Two independent 50 GbE channels with parallelism 16.
4 x 25G ethernet On or off On Four independent 25 GbE channels with parallelism 8.
Custom and Fracturable IP Core Parameters
Latency N/P+ (BM speed x R) +10; with BMspeed is 1, 2, 4 or 6. BMspeed is 4 The latency as a function of the Berlekamp–Massey (BM) speed (decoder only).
Favor ROM No or yes Yes Uses M20K memory to reduce the ALMs. Savings are significant with large parallelism.
Use true dual-port ROM No or yes Yes -
Refresh ROM content No or yes No The IP core continuously rewrites the ROM contents.
Use backpressure No or yes No Decoder only. When you select Yes, you can use the out_ready signal to assert when the source is ready, but this option might limit fMAX.
Hyper-optimisation Low, medium, high Low -
Decoder Output Signal Options
Output decoding failure On or off On Turns on out_decfail signal
Output error symbol count On of off On Turns on out_errors_out signal.
Output error symbol values On or off On Turns on out_errorvalues_out signal.
Output start and end of packet On or off. On Use Avalon-ST SOP and EOP signal to indicate start and end of packet
Level Two Title