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1. About the External Memory Interfaces Intel® Agilex™ 7 F-Series and I-Series FPGA IP
2. Design Example Quick Start Guide for External Memory Interfaces Intel® Agilex™ 7 F-Series and I-Series FPGA IP
3. Design Example Description for External Memory Interfaces Intel® Agilex™ 7 F-Series and I-Series FPGA IP
4. External Memory Interfaces Intel® Agilex™ 7 F-Series and I-Series FPGA IP Design Example User Guide Archives
5. Document Revision History for External Memory Interfaces Intel® Agilex™ 7 F-Series and I-Series FPGA IP Design Example User Guide
2.1. Creating an EMIF Project
2.2. Generating and Configuring the EMIF IP
2.3. Generating the Synthesizable EMIF Design Example
2.4. Generating the EMIF Design Example for Simulation
2.5. Simulation Versus Hardware Implementation
2.6. Simulating External Memory Interface IP With ModelSim
2.7. Pin Placement for Intel® Agilex™ 7 F-Series and I-Series EMIF IP
2.8. Compiling and Programming the Intel® Agilex™ 7 F-Series and I-Series EMIF Design Example
2.9. Generating a Design Example with the Calibration Debug Option
2.10. Generating a Design Example with the TG Configuration Option
2.11. Using the Design Example with the EMIF Debug Toolkit
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2.10. Generating a Design Example with the TG Configuration Option
The generated EMIF design example includes a traffic generator block (TG). By default, the design example uses a simple TG block (altera_tg_avl) which can only be reset in order to relaunch a hard-coded traffic pattern. If necessary, you may choose to enable a configurable traffic generator (TG2) instead.
In the configurable traffic generator (TG2) (altera_tg_avl_2), you can configure the traffic pattern in real time through control registers—meaning that you do not have to recompile the design to change or relaunch the traffic pattern. This traffic generator provides fine control over the type of traffic that it sends on the EMIF control interface. Additionally, it provides status registers that contain detailed failure information.