Intel® MAX® 10 User Flash Memory User Guide

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ID 683180
Date 8/30/2022
Public
Document Table of Contents
Document Table of Contents x
1. Intel® MAX® 10 User Flash Memory Overview 2. Intel® MAX® 10 UFM Architecture and Features 3. Intel® MAX® 10 UFM Design Considerations 4. Intel® MAX® 10 UFM Implementation Guides 5. On-Chip Flash Intel® FPGA IP Core References 6. Intel® MAX® 10 User Flash Memory User Guide Archive 7. Document Revision History for the Intel® MAX® 10 User Flash Memory User Guide
2. Intel® MAX® 10 UFM Architecture and Features x
2.1. UFM and CFM Array Size 2.2. UFM Memory Organization Map 2.3. UFM Block Diagrams 2.4. UFM Operating Modes
3. Intel® MAX® 10 UFM Design Considerations x
3.1. Guideline: UFM Power Supply Requirement 3.2. Guideline: Program and Read UFM with JTAG 3.3. Guideline: UFM Content Initialization 3.4. Guideline: Erase Before Program
4. Intel® MAX® 10 UFM Implementation Guides x
4.1. On-Chip Flash Intel® FPGA IP Core 4.2. UFM Avalon-MM Operating Modes 4.3. Flash Initialization Files
4.2. UFM Avalon-MM Operating Modes x
4.2.1. UFM Read Status and Control Register 4.2.2. UFM Write Control Register 4.2.3. UFM Program (Write) Operation 4.2.4. UFM Sector Erase Operation 4.2.5. UFM Page Erase Operation 4.2.6. UFM Read Operation 4.2.7. UFM Burst Read Operation
4.2.7. UFM Burst Read Operation x
4.2.7.1. UFM Data Incrementing Burst Read 4.2.7.2. UFM Data Wrapping Burst Read
5. On-Chip Flash Intel® FPGA IP Core References x
5.1. On-Chip Flash Intel® FPGA IP Core Parameters 5.2. On-Chip Flash Intel® FPGA IP Core Signals 5.3. On-Chip Flash Intel® FPGA IP Core Registers
5.3. On-Chip Flash Intel® FPGA IP Core Registers x
5.3.1. Sector Address
1. Intel® MAX® 10 User Flash Memory Overview
2. Intel® MAX® 10 UFM Architecture and Features
3. Intel® MAX® 10 UFM Design Considerations
4. Intel® MAX® 10 UFM Implementation Guides
5. On-Chip Flash Intel® FPGA IP Core References
6. Intel® MAX® 10 User Flash Memory User Guide Archive
7. Document Revision History for the Intel® MAX® 10 User Flash Memory User Guide

7. Document Revision History for the Intel® MAX® 10 User Flash Memory User Guide

Document Version Intel® Quartus® Prime Version Changes
2022.08.30 18.0
  • Updated additional details for .dat initialization files in Flash Initialization Files section.
2020.06.30 18.0
  • Updated the following tables and sections to include the specification for device 10M02SCU324:
    • Table: UFM and CFM Array Size
    • Table: Data Wrapping Support for Intel® MAX® 10 Devices
    • Intel MAX 10 User Flash Memory Overview
    • UFM Block Diagrams
2019.07.02 18.0 Updated the Program Operation in Serial Mode figure to provide the minimum, typical, and maximum values for the write address to UFM.
2018.12.28 18.0 Added 10M02 device support to the Incrementing Burst Read Operation for 10M02, 10M04, and 10M08 Devices in Parallel Mode figure.
2018.06.29 18.0
  • Beginning from the Intel® Quartus® Prime software version 18.0, the name of this IP core has been changed from Altera On-Chip Flash IP core to On-Chip Flash Intel® FPGA IP core.
  • Added a reference to the Programming Files Generation section of the Embedded Design Handbook for the initialization flash content.
  • Updated the Incrementing Burst Read Operation for 10M04 and 10M08 Devices in Parallel Mode figure.
  • Updated the Incrementing Burst Read Operation for 10M16 and 10M25 Devices in Parallel Mode figure.
  • Updated the Incrementing Burst Read Operation for 10M50 Devices in Parallel Mode figure.
  • Updated the Wrapping Burst Read Operation for 10M04 and 10M08 Devices figure.
  • Updated the Wrapping Burst Read Operation for 10M16 and 10M25 Devices figure.
  • Updated the Wrapping Burst Read Operation for 10M40 and 10M50 Devices figure.
Date Version Changes
February 2017 2017.02.21 Rebranded as Intel.
December 2016 2016.12.20
  • Updated the description for Altera On-Chip Flash bit offsets 5–9 that the IP core sets these bits based on the device, and configuration and access mode settings you specify during instantiation. These settings are fixed.
  • Updated the description for Altera On-Chip Flash bit offsets 22–27 to include clearer information about sector address.
  • Added Sector Address topic that provides details about converting sector address from byte addressing to bit addressing.
May 2016 2016.05.02
  • Added the typical and minimum UFM programming time in parallel mode.
  • Corrected the minimum UFM reset time in parallel mode to 250 ns.
  • Added links to archived versions of the MAX 10 User Flash Memory User Guide.
November 2015 2015.11.02
  • Added information about the supported flash initialization files.
  • Added serial interface support for 10M40 and 10M50 devices. The maximum frequency for MAX 10 devices is 7.25 MHz, except for 10M40 and 10M50 devices, which is 4.81 MHz.
  • Added parallel interface support for 10M02 devices. The maximum frequency for MAX 10 devices is 116 MHz, except for 10M02 devices, which is 7.25 MHz.
  • Changed instances of Quartus II to Intel® Quartus® Prime .
May 2015 2015.05.04
  • Changed write to industry-standard term program.
  • Added a note to the UFM and CFM Array Size section that the total UFM size is the maximum possible value, which is dependent on the selected mode.
  • Added design consideration information about the maximum slew rate requirement for power supply ramp down.
  • Added design consideration information about erasing the flash location before performing a program operation.
December 2014 2014.12.15
  • Added support for serial interface.
  • Added maximum operating frequency of 7.25 MHz for serial interface.
  • Updated the UFM block diagram to include serial interface.
  • Added design consideration information about creating initial memory content using the IP core, and programming UFM using JTAG interface version IEEE Standard 1149.1.
  • Added new timing diagrams for read and write operations in serial mode.
  • Added information for the new serial interface related GUI parameters, signals, and registers.
  • Added information for the following new Avalon-MM slave interface signals for serial mode: addr, read, readdata, write, writedata, waitrequest, readdatavalid, and burstcount.
  • Added information for the following new parameters:
    • Data Interface that allows you to choose between Parallel and Serial interface.
    • Configuration Scheme and Configuration Mode that replace Dual Images. The new parameters include all supported configuration modes.
    • Read Burst Count that allows the burst count width to be auto-adjusted.
September 2014 2014.09.22

Initial release.
Level Two Title