Intel® Cyclone® 10 LP Device Datasheet

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ID 683251
Date 10/31/2022
Public
Document Table of Contents
Document Table of Contents x
Intel® Cyclone® 10 LP Device Datasheet
Intel® Cyclone® 10 LP Device Datasheet x
Operating Conditions Power Consumption Switching Characteristics Configuration Specifications I/O Timing Glossary Document Revision History for the Intel® Cyclone® 10 LP Device Datasheet
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot or Undershoot Voltage Recommended Operating Conditions ESD Performance DC Characteristics I/O Standard Specifications
DC Characteristics x
Supply Current Bus Hold OCT Specifications Pin Capacitance Internal Weak Pull-Up and Weak Pull-Down Resistor Hot-Socketing Schmitt Trigger Input
I/O Standard Specifications x
Single-Ended I/O Standard Specifications Single-Ended SSTL and HSTL I/O Reference Voltage Specifications Single-Ended SSTL and HSTL I/O Standards Signal Specifications Differential SSTL I/O Standard Specifications Differential HSTL I/O Standard Specifications Differential I/O Standard Specifications
Switching Characteristics x
Core Performance Specifications Periphery Performance
Core Performance Specifications x
Clock Tree Specifications PLL Specifications Embedded Multiplier Specifications Memory Block Specifications
Periphery Performance x
High-Speed I/O Specifications Duty Cycle Distortion Specifications OCT Calibration Timing Specification IOE Programmable Delay
High-Speed I/O Specifications x
RSDS Transmitter Timing Specifications Emulated RSDS_E_1R Transmitter Timing Specifications Mini-LVDS Transmitter Timing Specifications True LVDS Transmitter Timing Specifications Emulated LVDS Transmitter Timing Specifications LVDS Receiver Timing Specifications
Configuration Specifications x
JTAG Timing Parameters Active Configuration Mode Specifications AS Configuration Timing Passive Configuration Mode Specifications PS Configuration Timing FPP Configuration Timing
Intel® Cyclone® 10 LP Device Datasheet

PS Configuration Timing

Table 40.  PS Configuration Timing Parameters for Intel® Cyclone® 10 LP Devices
Symbol Parameter Minimum Maximum Unit
1.2 V Core Voltage 1.0 V Core Voltage 1.2 V Core Voltage 1.0 V Core Voltage
tCF2CD nCONFIG low to CONF_DONE low — 500 ns
tCF2ST0 nCONFIG low to nSTATUS low — 500 ns
tCFG nCONFIG low pulse width 500 — ns
tSTATUS nSTATUS low pulse width 45 230 51 µs
tCF2ST1 nCONFIG high to nSTATUS high — 230 52 µs
tCF2CK nCONFIG high to first rising edge on DCLK 230 51 — µs
tST2CK nSTATUS high to first rising edge of DCLK 2 — µs
tDH Data hold time after rising edge on DCLK 0 — ns
tCD2UM CONF_DONE high to user mode 53 300 650 µs
tCD2CU CONF_DONE high to CLKUSR enabled 4 × maximum DCLK period — —
tCD2UMC CONF_DONE high to user mode with CLKUSR option on tCD2CU + (3,192 × CLKUSR period) — —
tDSU Data setup time before rising edge on DCLK 5 8 —
tCH DCLK high time 3.2 6.4 — — ns
tCL DCLK low time 3.2 6.4 — — ns
tCLK DCLK period 7.5 15 — — ns
fMAX DCLK frequency — — 133 66 MHz
Related Information
51 This value is applicable if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width.
52 This value is applicable if you do not delay configuration by externally holding the nSTATUS low.
53 The minimum and maximum numbers apply only if you choose the internal oscillator as the clock source for starting the device.
Level Two Title