Customizable Flash Programmer User Guide

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ID 683271
Date 4/28/2023
Public
Document Table of Contents
Document Table of Contents x
1. Customizable Flash Programmer Overview 2. Customizable Flash Programmer 3. Implementing the Customizable Flash Programmer 4. Document Revision History for the Customizable Flash Programmer User Guide
1. Customizable Flash Programmer Overview x
1.1. Device Family Support 1.2. Software Support
2. Customizable Flash Programmer x
2.1. Programmer Image 2.2. System Console TCL Script 2.3. Limitations and Restrictions
3. Implementing the Customizable Flash Programmer x
3.1. Generating the Raw Programming Data File (.rpd) from User Design 3.2. Compiling the Programmer Image Project and Generating the .sof File 3.3. Customizing the TCL Script 3.4. Programming the Flash Using the System Console
3.1. Generating the Raw Programming Data File (.rpd) from User Design x
3.1.1. Understanding Quad SPI Flash Byte-Addressing 3.1.2. Understanding Dummy Clock Cycles for Single and Quad IO Fast Read 3.1.3. Generating the .rpd File Using the Convert Programming File Tool
3.1.3. Generating the .rpd File Using the Convert Programming File Tool x
3.1.3.1. Generating .rpd File for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices 3.1.3.2. Generating .rpd File for Other FPGA Devices
3.2. Compiling the Programmer Image Project and Generating the .sof File x
3.2.1. Configuring the IP Cores Setting 3.2.2. Assigning External Clock Source for the IP Cores 3.2.3. Generating the Programmer Image .sof File from the Reference Project
3.2.1. Configuring the IP Cores Setting x
3.2.1.1. Configuring JTAG to Avalon® Master Bridge IP Core 3.2.1.2. Configuring Intel AvMM Bursting Master IP Core 3.2.1.3. Configuring Generic Serial Flash Interface IP Core
3.3. Customizing the TCL Script x
3.3.1. TCL Script Structures 3.3.2. TCL Script User Setting 3.3.3. Customizing the Programming Flow 3.3.4. Creating Custom Functions
3.4. Programming the Flash Using the System Console x
3.4.1. Executing Commands in the System Console 3.4.2. Executing the System-Console Commands in the Nios® II Command Shell
1. Customizable Flash Programmer Overview
2. Customizable Flash Programmer
3. Implementing the Customizable Flash Programmer
4. Document Revision History for the Customizable Flash Programmer User Guide

3.1.1. Understanding Quad SPI Flash Byte-Addressing

The flash devices usually support one or both of the following byte-addressing modes:

  • 3-byte addressing
  • 4-byte addressing
Note: Refer to the third-party quad SPI flash datasheet for the byte-addressing modes supported for your flash devices.

The flash device reads either 24-bit (3-byte) address or 32-bit (4-byte) address before the flash device starts taking data to write to the flash memory, or output the data if the flash device receives a read command.

Figure 2. Reading Configuration Data from Flash with 3-Byte and 4-Byte Addressing
Table 2.  Byte-Addressing Requirement for Intel FPGAs
FPGA Devices Required Power Up Byte-Addressing of the Flash Devices
Legacy device older than 28nm devices, Intel® Cyclone® 10 LP 3-byte addressing
Cyclone® V, Arria® V, Stratix® V
  • 3-byte addressing (limited memory address access)
  • 4-byte addressing
Intel® Arria® 10, Intel® Cyclone® 10 GX 4-byte addressing

For example, if your flash device does not support power up 4-byte addressing mode, you cannot use your flash device for the Intel® Arria® 10 and Intel® Cyclone® 10 GX configuration.

Flash devices with density more than 128 megabits (Mb) require 4-byte address to access the memory space higher than 128 Mb. For flash devices that do not support non-volatile 4-byte addressing setting, the FPGA is unable to read the configuration image that has the start address beyond 128 Mb and unable to store image beyond 128Mb for Remote System Update application.

Figure 3. Memory Space of a 256 Mb Flash
Level Two Title