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1. Intel® High Level Synthesis Compiler Standard Edition User Guide
2. Overview of the Intel® High Level Synthesis (HLS) Compiler Standard Edition
3. Creating a High-Level Synthesis Component and Testbench
4. Verifying the Functionality of Your Design
5. Optimizing and Refining Your Component
6. Simulating Your Design
7. Synthesize your Component with Intel® Quartus® Prime Standard Edition
8. Integrating your IP into a System
A. Reviewing the High Level Design Reports (report.html)
B. Limitations of the Intel® HLS Compiler Standard Edition
C. Intel® HLS Compiler Standard Edition User Guide Archives
D. Document Revision History for Intel® HLS Compiler Standard Edition User Guide
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A.4. Reviewing Component Area Usage
The High Level Design Report (report.html) provides a detailed breakdown of the estimated FPGA area usage.
The estimated area usage information correlates with, but does not necessarily match, the resource usage results from the Intel® Quartus® Prime Standard Edition software. Use the estimated area usage to identify parts of the design with large area overhead. You can also use the estimates to compare area usage between different designs. Do not use the estimated area usage information for final resource utilization planning.
The Quartus Fit Summary section of the High Level Design Report Summary page is populated after compiling your design with Intel® Quartus® Prime software. After that compilation, the following sections appear on the Summary page:
- Quartus Fit Clock Summary
- Quartus Fit Resource Utilization Summary
The Quartus Fit Clock Summary section shows the maximum clock frequencies that can be achieved for the design.
The Quartus Fit Resource Utilization Summary section shows the total area utilization both for the entire design, and for each component individually. There is no breakdown of area information by source line.
Tip: Compiling your component using the Intel® Quartus® Prime software might take several hours. In contrast, the Intel® HLS Compiler can generate the High Level Design Report in minutes for most designs.
Before compiling your design with Intel® Quartus® Prime software, the High Level Design Report looks like the following example:
After compiling your design with Intel® Quartus® Prime software, the High Level Design Report looks like the following example. The Quartus Fit Summary section is now populated.
