Video and Image Processing Suite User Guide

ID 683416
Date 2/12/2021
Public

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25.4. Avalon-ST Video Stream Cleaner Control Registers

You may choose to enable an Avalon-MM control slave interface for the Avalon-ST Video Stream Cleaner IP core.
Table 84.  Avalon-ST Video Stream Cleaner Control RegistersThe table below describes the control register map that controls the Avalon-ST Video Stream Cleaner IP core. Internally the IP core tracks the number of times that various error conditions the IP core encounters and repaired or removed. You can use the control slave interface to read and reset these values.
Address Register Description
0 Control Bit 0 of this register is the Go bit, all other bits are unused.

Setting this bit to 0 causes the Avalon-ST Video Stream Cleaner IP core to stop at the end of the next frame or field packet.

1 Status Bit 0 of this register is the Status bit, all other bits are unused.

The IP core sets this address to 0 between frames. It is set to 1 while the IP core is processing data and cannot be stopped.

2 Interrupt This bit is not used because the IP core does not generate any interrupts.
3 Non modulo width count Counts the number of frames with widths that are non-integer multiples of the modulo width check value.
4 Width too small count Counts the number of frames with preceding control packets with widths smaller than the value you set for the Minimum frame width parameter.
5 Width too big count Counts the number of frames with preceding control packets with widths greater than the value you set for the Maximum frame width parameter.
6 Height too small count Counts the number of frames with preceding control packets with heights smaller than the value you set for the Minimum frame height parameter.
7 Height too big count Counts the number of frames with preceding control packets with heights greater than the value you set for the Maximum frame height parameter.
8 No valid control packet count Counts the number of frames with no valid preceding control packet.
9 Interlaced greater than 1080i count Counts the number of fields with content greater than 1080i.
10 Mismatch pad frame count Counts the number of frame packets that have been padded to match the length implied by the control packet.
11 Mismatch crop frame count Counts the number of frame packets that have been cropped to match the length implied by the control packet.
12 Counter reset Writing any value to this register will reset all error count values to 0.