2.11.17. Clocks

E-Tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

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Date 2/02/2024

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2.11.17. Clocks

You must set the transceiver reference clock (i_clk_ref) frequency to a value that the IP supports.

The Synchronous Ethernet standard, described in the ITU-T G.8261, G.8262, and G.8264 recommendations, requires that the TX clock be filtered to maintain synchronization with the RX reference clock through a sequence of nodes. The expected usage is that user logic drives the transceiver reference clocks with a filtered version of the RX recovered clock signal, to ensure the receive and transmit functions remain synchronized. In this usage model, a design component outside the E-Tile Hard IP for Ethernet Intel FPGA IP performs the filtering.

An alternate clocking arrangement for i_clk_ref can be used to enable the Synchronous Ethernet (SyncE) operation. Two or more channels can share the Off-chip Cleanup PLL clock output. The Primary SyncE clock and the Backup SyncE clock come from the recovered clock output pins of channels connected to the same SyncE network while i_clk_ref connects to the cleanup PLL. SyncE clocking can be also combined with the data path clocking.

Figure 56. Clock Connection in SyncE Operation

SyncE mode, with dedicated reference clock for each channel, is supported when you turn on Enable SyncE With Dedicated Reference Clock Per Channel for single/multiple 10G and 25G Ethernet channels. When this parameter is enabled, Enable external AIB clocking and Enable RS-FEC options are still available but Enable Custom Rate option is disabled as custom cadence connection is done internally.

When Enable SyncE With Dedicated Reference Clock Per Channel is enabled, TX elastic FIFO (eFIFO) is instantiated within the IP. The number of TX eFIFO generated is based on the number of 10G/25G Ethernet channels. The write clock of the eFIFO is o_clk_pll_div66 from TX PMA while the read clock is i_sl_clk_tx input clock and the FIFO has a depth of 32. The write data valid signal of the FIFO is connected to the custom cadence port of the hard IP, hence the write data valid is driven high for 32 write clocks and low for 1 clock cycle.

Table 58. Clock InputsDescribes the input clocks that you must provide.
Signal Name	Description
`i_sl_clk_tx`	This clock drives both, the TX datapath and TX interface, for 10G/25G channel. Frequency of 402.83203125 MHz for all modes on a 25G channel. Also applicable for 10G channels when overclocked or when PTP is enabled. Frequency of 161.1328125 MHz for all modes on a 10G channel except for enabled PTP. This clock must be active during dynamic reconfiguration. Note: Applicable only when you select Single 10GE/25GE.
`i_sl_clk_rx`	This clock drives both, the RX datapath and TX interface, for 10/25G channel. Frequency of 402.83203125 MHz for all modes on a 25G channel. Also applicable for 10G channels when overclocked or when PTP is enabled. Frequency of 161.1328125 MHz for all modes on a 10G channel except for enabled PTP. This clock must be active during dynamic reconfiguration. Note: Applicable only when you select Single 10GE/25GE.
`i_sl_clk_tx[n]`	These clocks drive the active TX datapath and TX interface for 10/25G channel when Asynchronous mode is disabled. These clocks drive the active TX datapath for 10/25G channel when Asynchronous mode is enabled while `i_sl_async_clk_tx` clocks the TX interface. Each channel has its own clock input. Frequency of 402.83203125 MHz for all modes on a 25G channel. Also applicable for 10G channels when overclocked or when PTP is enabled. Frequency of 161.1328125 MHz for all modes on a 10G channel except for enabled PTP. This clock must be active during dynamic reconfiguration. Note: Applicable only when you select 1 to 4 10GE/25GE with optional RS-FEC or 100GE or 1 to 4 10GE/25GE with optional RS-FEC and 1588 PTP.
`i_sl_clk_rx[n]`	These clocks drive the active RX datapath and RX interface for 10/25G channel when Asynchronous mode is disabled. These clocks drive the active RX datapath for 10/25G channel when Asynchronous mode is enabled while `i_sl_async_clk_rx` clocks the RX interface.. Each channel has its own clock input. Frequency of 402.83203125 MHz for all modes on a 25G channel. Also applicable for 10G channels when overclocked or when PTP is enabled. Frequency of 161.1328125 MHz for all modes on a 10G channel except for enabled PTP. This clock must be active during dynamic reconfiguration. Note: Applicable only when you select 1 to 4 10GE/25GE with optional RS-FEC or 100GE or 1 to 4 10GE/25GE with optional RS-FEC and 1588 PTP.
`i_clk_tx`	This clock drives the TX interface for 100G channel. The frequency of this clock is 402.83203125 MHz for all modes on a 100G channel RS-FEC(544,514) modes, where the frequency is 415.0390625 MHz. Note: Applicable only when you select Single 100GE with optional RS-FEC or 100GE or 1 to 4 10GE/25GE with optional RS-FEC and 1588 PTP. This port is disabled and replaced by `i_aib_clk` when External AIB clocking is selected.
`i_clk_rx`	This clock drives the RX interface for 100G channel. The frequency of this clock is 402.83203125 MHz for all modes on a 100G channel RS-FEC(544,514) modes, where the frequency is 415.0390625 MHz. Note: Applicable only when you select Single 100GE with optional RS-FEC or 100GE or 1 to 4 10GE/25GE with optional RS-FEC and 1588 PTP. This port is disabled and replaced by `i_aib_clk` when External AIB clocking is selected
`i_clk_ref`	The input clock `i_clk_ref` is the reference clock for the high-speed serial clocks and the datapath parallel clocks. This clock must have the following frequencies with a ±100 ppm accuracy per the IEEE 802.3-2015 Ethernet Standard: 156.25 MHz (10G/25G/100G) 322.265625 MHz (10G/25G/100G) 312.500000 MHz (100G) 644.531250 MHz (100G) Variants with (544,514) RSFEC option only support 156.25 MHz and 312.5 MHz PHY `i_clk_ref` reference frequency. The reference clock must be at 156.25 MHz frequency to support Auto Negotiation and Link Training. In addition, `i_clk_ref` must meet the jitter specification of the IEEE 802.3-2015 Ethernet Standard The PLL and clock generation logic use this reference clock to derive the transceiver and PCS clocks. The input clock should be a high quality signal on the appropriate dedicated clock pin. Refer to the Intel® Stratix® 10 Device Data Sheet or Intel® Agilex™ 7 Device Data Sheet for transceiver reference clock phase noise specifications. When using this clock for Synchronous Ethernet, the expected usage is that this signal being driven by a filtered and divided version of `o_clk_rec_div64` or `o_clk_rec_div66`, to ensure the receive and transmit functions remain synchronized. Therefore, you must include an additional component on your board. The IP core does not provide filtering. Note: Applicable only when you select Single 100GE with optional RS-FEC or 100GE or 1 to 4 10GE/25GE with optional RS-FEC and 1588 PTP.
`i_reconfig_clk`	Avalon® clock for the E-Tile Hard IP for Ethernet Intel FPGA IP transceiver reconfiguration interface, RS-FEC reconfiguration interface, PTP reconfiguration interface, and Ethernet reconfiguration interface. The clock frequency is 100-125 MHz. All reconfiguration interface signals are synchronous to `i_reconfig_clk`. Note: When you turn on Enable AN/LT or select any 10G/25G channel variant in the Select Core Variant, `i_reconfig_clk` is set to 500 MHz in simulation to accelerate IP's simulation. `i_reconfig_clk` is asynchronous to other clocks in the IP. For an example of clock constraints implementation, please refer to Synopsys Design Constraints (.sdc) file generated with the example design.
`i_aib_clk`	This clock is used for all internal datapath provided externally by user. This clock must be driven by a clock running at the fastest line rate in the design divided by 64 and must be frequency locked to `i_aib_2x_clk` clock. Phase offset between these two clocks are allowed. Note: Applicable only when you select Enable external AIB clocking parameter in 10/25/100GE variants.
`i_aib_2x_clk`	This clock must have double the frequency of `i_aib_clk` clock and is provided externally by user. It is used for clock crossing handling in EMIB interface. This clock must be frequency locked to `i_aib_clk` clock. Phase offset between these two clocks are allowed. Note: Applicable only when you select Enable external AIB clocking parameter in 10/25/100GE variants.
`i_sl_async_clk_tx[n]`	This clock drives the TX interface for 25G channel when Asynchronous mode is enabled. The clock frequency must be within 390.625 MHz to 402.83203125 MHz. Note: Applicable only when you select Enable asynchronous adapter clocks parameter.
`i_sl_async_clk_rx[n]`	This clock drives the RX interface for 25G channel when Asynchronous mode is enabled. The clock frequency must be within 390.625 MHz to 402.83203125 MHz. Note: Applicable only when you select Enable asynchronous adapter clocks parameter.
`i_sl_clk_tx_tod[n-1:0]`	TX interface Time Of Day (ToD) Clock. The `o_clk_pll_div66[n-1:0]` must drive this clock. The clock frequency varies based on the Ethernet variant: 156.25 MHz (10G) 390.625 MHz (25G) Note: Applicable only when you set the PTP Accuracy Mode parameter to Advanced Mode. For more information, refer to the PTP Timestamp Accuracy section.
`i_sl_clk_rx_tod[n-1:0]`	RX interface Time Of Day (ToD) Clock. The `o_clk_rec_div66[n-1:0]` must drive this clock. The clock frequency varies based on the Ethernet variant: 156.25 MHz (10G) 390.625 MHz (25G) Note: Applicable only when you set the PTP Accuracy Mode parameter to Advanced Mode. For more information, refer to the PTP Timestamp Accuracy section.
`i_clk_ptp_sample`	Sample clock for PTP measurement. This is an external clock provided to the design with frequency of 114.285714 MHz (with required period of 8.75 ns) with ± 100 ppm. Note: Applicable only when you set the PTP Accuracy Mode parameter to Advanced Mode. For more information, refer to the PTP Timestamp Accuracy section.

Table 59. Clock OutputsDescribes the output clocks that the IP core provides. In most cases these clocks participate in internal clocking of the IP core as well.
Signal Name	Description
`o_clk_pll_div64[n]`	Hard IP for Ethernet block clock. Supports the following clock frequencies: 402.83203125 MHz for 25G and 100G with optional RS-FEC(528,514) channels 402.83203125 MHz for 10G PTP and 25G PTP channels 415.0390625 MHz for 100G with RS-FEC(544,514) channel 161.1328125 MHz for 10G channels This clock is reliable only after `o_tx_pll_locked` is asserted.
`o_clk_pll_div66[n]`	Hard IP for Ethernet block clock times 64/66. Supports the following clock frequencies: 390.625 MHz for 25G and 100G with optional RS-FEC(528,514) channels 402.4621 MHz for 100G with RS-FEC(544,514) 156.25 MHz for 10G channels This clock is reliable only after `o_tx_pll_locked` is asserted.
`o_clk_rec_div64[n]`	Derived from RX recovered clock. This clock supports the SyncE standard. The RX recovered clock frequency is: 161.1328125 MHz ±100 ppm for 10G channels 402.83203125 MHz ±100 ppm for 25G channels 402.83203125 MHz ±100 ppm for 100G with optional RS-FEC(528,514) channels 415.0390625 MHz ±100 ppm for 100G with RS-FEC(544,514) channels This clock is reliable only after `o_cdr_lock[n]` is asserted. When using this clock for Synchronous Ethernet, the expected usage is that you drive the TX transceiver reference clock with a filtered and divided version of `o_clk_rec_div64` or `o_clk_rec_div66`, to ensure the receive and transmit functions remain synchronized. To do so you must include an additional component on your board. The IP core does not provide filtering. Note: The RX recovered clock is not available for PTP channels when PTP enabled.
`o_clk_rec_div66[ch]`	Derived from RX recovered clock. This clock supports the Synchronous Ethernet standard. The RX recovered clock frequency is: 156.25 MHz ±100 ppm for 10G channels 390.625 MHz ±100 ppm for 25G channels 390.625 MHz ±100 ppm for 100G with optional RS-FEC(528,514) channels 402.4621 MHz ±100 ppm for 100G with optional RS-FEC(528,514) channels This clock is reliable only after `o_cdr_lock[n]` is asserted. When using this clock for Synchronous Ethernet, the expected usage is that you drive the TX transceiver PLL reference clock with a filtered and divided version of `o_clk_rec_div64` or `o_clk_rec_div66`, to ensure the receive and transmit functions remain synchronized. To do so you must include an additional component on your board. The IP core does not provide filtering. Note: The RX recovered clock is not available for PTP channels when PTP enabled.

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E-Tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

2.11.17. Clocks