Intel® Stratix® 10 General Purpose I/O User Guide

ID 683518
Date 9/13/2023
Public
Document Table of Contents

5.1. GPIO Intel® FPGA IP Parameter Settings

You can set the parameter settings for the GPIO IP in the Intel® Quartus® Prime software. There are three groups of options: General, Buffer, and Registers.
Table 25.   GPIO IP Parameters—General
Parameter Condition Allowed Values Description
Data Direction
  • Input
  • Output
  • Bidir

Specifies the data direction for the GPIO.

Data width

1 to 128

Specifies the data width.

Use legacy top-level port names
  • On
  • Off

Use same port names as in Stratix® V, Arria® V, and Cyclone® V devices.

For example, dout becomes dataout_h and dataout_l, and din becomes datain_h and datain_l.

Note: The behavior of these ports are different than in the Stratix® V, Arria® V, and Cyclone® V devices. For the migration guideline, refer to the related information.
Table 26.   GPIO IP Parameters—Buffer
Parameter Condition Allowed Values Description
Use differential buffer
  • On
  • Off

If turned on, enables differential I/O buffers.

Use pseudo differential buffer
  • Data Direction = Output
  • Use differential buffer = On
  • On
  • Off

If turned on in output mode, enables pseudo differential output buffers.

This option is automatically turned on for bidirectional mode if you turn on Use differential buffer.

Enable output enable port Data Direction = Output
  • On
  • Off

If turned on, enables user input to the OE port. This option is automatically turned on for bidirectional mode.

In Intel® Stratix® 10 devices, each 3 V I/O bank supports only two output enables (OE) for its eight single-ended I/Os.

Table 27.   GPIO IP Parameters—Registers
Parameter Condition Allowed Values Description
Register mode
  • None
  • Simple register
  • DDIO

Specifies the register mode for the GPIO IP:

  • None—specifies a simple wire connection from/to the buffer.
  • Simple register—specifies that the DDIO is used as a simple register in single data-rate mode (SDR). The Fitter may pack this register in the I/O.
  • DDIO— specifies that the IP core uses the DDIO.

If you use an I/O standard supported only by the 3 V I/O banks, select None.

Enable synchronous clear / preset port Register mode = DDIO
  • None
  • Clear
  • Preset

Specifies how to implement synchronous reset port.

  • None—Disables synchronous reset port.
  • Clear—Enables the SCLR port for synchronous clears.
  • Preset—Enables the SSET port for synchronous preset.
Enable asynchronous clear / preset port Register mode = DDIO
  • None
  • Clear
  • Preset

Specifies how to implement asynchronous reset port.

  • None—Disables asynchronous reset port.
  • Clear—Enables the ACLR port for asynchronous clears.
  • Preset—Enables the ASET port for asynchronous preset.

ACLR and ASET signals are active high.

Enable clock enable ports Register mode = DDIO
  • On
  • Off
  • On—exposes the clock enable (CKE) port to allow you to control when data is clocked in or out. This signal prevents data from being passed through without your control.
  • Off—clock enable port is not exposed and data always pass through the register automatically.
Separate input/output Clocks
  • Data Direction = Bidir
  • Register mode = Simple register or DDIO
  • On
  • Off
If turned on, enables separate clocks (CK_IN and CK_OUT) for the input and output paths in bidirectional mode.