AN 820: Hierarchical Partial Reconfiguration over PCI Express* Reference Design for Intel® Stratix® 10 Devices

ID 683531
Date 9/24/2018
Public
Document Table of Contents

1.5.3.2. Programming the Design Using Example Applications

The following steps describe programming your design using the provided scripts:

  1. Program the base revision .sof file using the programmer. Power cycle the host PC to allow the PCIe* link to enumerate. To ensure that the FPGA shows up as a PCIe* device, type the following from the Linux shell:
    lspci -vvvd1172:
  2. To verify the functionality of the design, type the following from the Linux shell:
    ./example_host_uio
  3. To replace the parent PR partition in the design with any of the following single function PR persona, type the following from the Linux shell:
    fpga-configure -p <rbf file from list> 10000
    where <rbf file from list> is one of the following files:
    • s10_pcie_devkit_cvp_normal_basic_arithmetic.pr_partition
    • s10_pcie_devkit_cvp_normal_basic_dsp.pr_partition
    • s10_pcie_devkit_cvp_normal_ddr4_access.pr_partition
    • s10_pcie_devkit_cvp_normal_gol.pr_partition
  4. To verify the functionality of the design, type the following from the Linux shell:
    ./example_host_uio
  5. To program a parent PR partition that contains two child partitions, type the following from the Linux shell:
    fpga-configure -p s10_pcie_devkit_cvp_ddr4_access.pr_partition.rbf 10000
    					
    Both child partitions are DDR4 access personas.
  6. To verify the functionality of the design, type the following from the Linux shell:
    ./example_host_uio
  7. Further, you can reprogram each of the child PR partitions with any combination of personas. The following are the files generated in the output_files directory:
    • s10_pcie_devkit_cvp_ddr4_access.pr_partition.pr_child_partition_1.rbf
    • s10_pcie_devkit_cvp_basic_dsp.pr_partition.pr_child_partition_0.rbf
    • s10_pcie_devkit_cvp_basic_dsp.pr_partition.pr_child_partition_1.rbf
    • s10_pcie_devkit_cvp_basic_arithmetic.pr_partition.pr_child_partition_0.rbf
    • s10_pcie_devkit_cvp_basic_arithmetic.pr_partition.pr_child_partition_1.rbf
    • s10_pcie_devkit_cvp_gol.pr_partition.pr_child_partition_0.rbf
    • s10_pcie_devkit_cvp_gol.pr_partition.pr_child_partition_1.rbf
    Each bitstream file is unique to the particular child PR region, and not interchangeable. For example, *.pr_child_partition_0.rbf file is only compatible with child PR region 0, and not 1.
  8. To program each child region, type the following in the Linux shell:
    For child region 0:
    fpga-configure -p <persona>.pr_partition.pr_child_partition_0.rbf 10
    For child region 1:
    fpga-configure -p <persona>.pr_partition.pr_child_partition_1.rbf 20

    The PR region controller for the larger parent PR region is at address 0x10000. The PR region controller for the two smaller child PR regions is at addresses 0x10 and 0x20 respectively.