Intel® Stratix® 10 Analog to Digital Converter User Guide

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ID 683612
Date 2/09/2021
Public
Document Table of Contents
Document Table of Contents x
1. Intel® Stratix® 10 ADC Overview 2. Intel® Stratix® 10 ADC Architecture and Features 3. Intel® Stratix® 10 ADC Design Considerations 4. Intel® Stratix® 10 ADC Implementation Guides 5. Intel® Stratix® 10 ADC IP Core References 6. Intel® Stratix® 10 Analog to Digital Converter User Guide Archives 7. Document Revision History for the Intel® Stratix® 10 Analog to Digital Converter User Guide
1. Intel® Stratix® 10 ADC Overview x
1.1. Release Information for Voltage Sensor and Temperature Sensor Intel® FPGA IP Cores
2. Intel® Stratix® 10 ADC Architecture and Features x
2.1. Intel® Stratix® 10 Voltage Sensor 2.2. Intel® Stratix® 10 Temperature Sensing Diodes
2.1. Intel® Stratix® 10 Voltage Sensor x
2.1.1. Voltage Conversion
2.2. Intel® Stratix® 10 Temperature Sensing Diodes x
2.2.1. Internal Temperature Sensor 2.2.2. External Temperature Sensor 2.2.3. Temperature Sensor Channels and Locations 2.2.4. Temperature Sensor Error Codes
2.2.1. Internal Temperature Sensor x
2.2.1.1. Temperature Calculation for the Internal Temperature Sensor
3. Intel® Stratix® 10 ADC Design Considerations x
3.1. Guidelines: Selecting Temperature Sensing Chip to Interface with the Intel® Stratix® 10 External TSD 3.2. Guidelines: Using External Temperature Sensors 3.3. Guidelines: Calibrate Temperature Sensing Chip Interfacing the Intel® Stratix® 10 External TSD
4. Intel® Stratix® 10 ADC Implementation Guides x
4.1. Sampling the Intel® Stratix® 10 Voltage Sensor Channels 4.2. Reading the Intel® Stratix® 10 Internal Temperature Sensing Diodes
5. Intel® Stratix® 10 ADC IP Core References x
5.1. Voltage Sensor Intel® FPGA IP Digital Signals 5.2. Temperature Sensor Intel® FPGA IP Digital Signals
1. Intel® Stratix® 10 ADC Overview
2. Intel® Stratix® 10 ADC Architecture and Features
3. Intel® Stratix® 10 ADC Design Considerations
4. Intel® Stratix® 10 ADC Implementation Guides
5. Intel® Stratix® 10 ADC IP Core References
6. Intel® Stratix® 10 Analog to Digital Converter User Guide Archives
7. Document Revision History for the Intel® Stratix® 10 Analog to Digital Converter User Guide

2.2.3. Temperature Sensor Channels and Locations

The Intel® Stratix® 10 internal TSDs are located in the core fabric, transceiver tiles, and HBM2 stacks. The external TSDs are available in the core fabric and transceiver tiles.
  • To read the internal TSDs, specify the channels to sample in the cmd_data signal to the Temperature Sensor IP core.
  • To read the external TSDs, connect external temperature sensors to the designated TEMPDIODE pin.
Figure 5. Locations and Channel Numbers of Intel® Stratix® 10 TSDsThis diagram shows the temperature sensor channel locations from a package bottom view. Each transceiver tile in the diagram is labeled using the bank number of one of its transceiver banks.


Note: The availability of the transceiver tiles and HBM2 stacks varies among Intel® Stratix® 10 devices. To identify the location—and availability—of a transceiver tile, find the location of one of its transceiver banks in the Intel® Quartus® Prime Pin Planner. For example, in the Intel® Stratix® 10 GX 400, TX 400, or SX 400 device, the internal TSD channels are CH0 for the core fabric and CH1 for the single transceiver tile.
Table 3.  Internal TSD Channels and External TSD Pins
Internal TSD Channel External TSD
Pin Device and Package Support
CH0

TEMPDIODEp[0]

TEMPDIODEn[0]

All Intel® Stratix® 10 devices and packages.
CH1

TEMPDIODEp[1]

TEMPDIODEn[1]

All Intel® Stratix® 10 devices and packages.
CH2

TEMPDIODEp[2]

TEMPDIODEn[2]

Support of these external TSDs depends on availability of the transceiver tile.

However, regardless of transceiver tile availability, these external TSDs are not supported in the NF43, UF50, and HF55 packages of the following devices:

  • GX 850 and SX 850
  • GX 1100 and SX 1100
  • GX 1650 and SX 1650
  • GX 2100 and SX 2100
  • GX 2500 and SX 2500
  • GX 2800 and SX 2800
  • GX 4500 and SX 4500
  • GX 5500 and SX 5500

For the listed devices, use the Temperature Sensor IP core to read the internal TSD channels.

CH3

TEMPDIODEp[3]

TEMPDIODEn[3]

CH4

TEMPDIODEp[4]

TEMPDIODEn[4]

CH5

TEMPDIODEp[5]

TEMPDIODEn[5]

CH6

TEMPDIODEp[6]

TEMPDIODEn[6]

CH7 — The high-bandwidth DRAM memory (HBM2) stacks do not feature external TSDs. Use the internal TSD channels.
CH8 —
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