Differences Among Intel SoC Device Families

ID 683648
Date 8/22/2018
Public

Document Revision History

Table 8.  Revision History for Differences Among Intel SoC Device Families
Date Version Changes
August 2018 2018.08.22 Corrections in Booting and Configuration Differences:
  • NAND configuration not supported by Intel® Stratix® 10 SoC
  • FPP configuration in Intel® Stratix® 10 SoC based on Avalon® -ST
April 2018 2018.04.11 Correction in "HPS SDRAM Controller Subsystem Differences": LPDDR3 not supported in the Intel® Stratix® 10 SoC
May 2017 2017.05.06 Additional detail about:
  • MPU ACP support
  • MPU cache error correction
  • Clock implementation
  • Stratix 10 security features
  • HPS-FPGA bridge latency support
  • Supported NAND flash memory widths
  • USB 2.0 OTG PHY connections
  • Corrected EMAC IP version number
  • EMAC FIFO sizes
  • EMAC I/O bank usage
  • EMAC RGMII-ID support
  • Details about SPI controller frame sizes, clocks, bit rates, and slave select
  • UART compatibility features
November 2016 2016.11.11
  • Added Stratix 10 SoC information
  • Reorganized for easier reference
  • Added IP version numbers for some third-party components
  • Added details about I/O configuration differences
  • Added booting and configuration differences

August 2014

2014.08.18

Updated Arria 10 SoC information
January 2014 2014.01.15

Initial release.