AN 810: Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report

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ID 683657
Date 12/18/2017
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Document Table of Contents
Document Table of Contents x
Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report
Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report x
Hardware Requirements Hardware Setup Hardware Checkout Methodology Deterministic Latency (Subclass 1) JESD204B IP Core and ADC Configurations Test Results Test Result Comments Document Revision History for AN 810: Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report Appendix
Hardware Checkout Methodology x
Receiver Data Link Layer Receiver Transport Layer Descrambling
Receiver Data Link Layer x
Code Group Synchronization (CGS) Initial Frame and Lane Synchronization (ILA)
Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report

Appendix

Timing Closure Details

To achieve timing closure, the following Synthesis and Fitter settings are used. Some of the settings used, varies with each JESD configuration design (e.g., Fitter seed value 1-10).

Table 10.  Synthesis and Fitter Settings of Quartus
Compiler setting Value used Default value
Router Timing Optimization Level MAXIMUM Normal
Spectra-Q Physical Synthesis On Off
Programmable Power Technology Optimization Force All Tiles with Failing Timing Paths to High Speed Automatic
Auto Packed Registers Sparse Auto Auto
Fitter Effort Standard Fit Auto Fit
Logic Cell Insertion - Logic Duplication On Auto
Optimization Technique Speed Balanced
Fitter Initial Placement Seed 1-10 1
Placement effort multiplier 1.0-8.0 1.0
Optimization mode Aggressive/High effort/Balanced Balanced

Device Used and Quartus Tool Version

For interoperability with ADC AD9208, two device variants of Intel® Arria® 10 are used.

  • For lane rates above 15G and up to 16G: 10AX115S1F45I1SG (Transceiver speed grade -1 device)
  • For lane rates of 15G and lower: 10AX115S2F45I2SG (Transceiver speed grade -2 device)

Intel® Quartus® Prime Version 16.1.1 Build 200 Standard Edition is used for compilation of designs.

PMA Settings Used

Using default PMA settings leads to erroneous link operation.

To get an error free link with AD9208, the following PMA parameters were adjusted as shown in the table below:

Note: No PMA settings on AD9208 ADC are modified.
PMA setting (as in QSF assignments) Value used
Receiver High Gain Mode Equalizer DC Gain Control NO_DC_GAIN
Receiver High Gain Mode Equalizer AC Gain Control

1-2

(‘2’ is used only for LMF=882/884 modes)
VCCR_GXB/VCCT_GXB Voltage 1.0 V
Receiver High Data Rate Mode Equalizer OFF

Additional JESD modes supported by ADC

The modes enlisted here have not been validated in this IOT, but they are supported by the ADC. These have been tabulated here for future reference.

L M F S N N' Comments
1 8 16 1 14 16 F=16 configuration is not supported by transport layer of Intel example design.
1 1 1 1 8 8

N’=8 configuration is not supported by transport layer of Intel example design

1 1 2 2 8 8
2 1 1 2 8 8
2 1 2 4 8 8
2 1 4 8 8 8
4 1 1 4 8 8
4 1 2 8 8 8
1 2 2 1 8 8
2 2 1 1 8 8
2 2 2 2 8 8
4 2 1 2 8 8
4 2 2 4 8 8
4 2 4 8 8 8
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