AN 837: Design Guidelines for HDMI Intel FPGA IP

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ID 683677
Date 1/28/2019
Public
Document Table of Contents
Document Table of Contents x
1. Design Guidelines for HDMI Intel® FPGA IP 2. Document Revision History for AN 837: Design Guidelines for HDMI Intel® FPGA IP
1. Design Guidelines for HDMI Intel® FPGA IP x
1.1. HDMI Intel® FPGA IP Design Guidelines 1.2. HDMI Intel® FPGA IP Board Design Tips 1.3. Schematic Diagrams 1.4. Hot-Plug Detect (HPD) 1.5. HDMI Intel® FPGA IP Display Data Channel (DDC)
1. Design Guidelines for HDMI Intel® FPGA IP
2. Document Revision History for AN 837: Design Guidelines for HDMI Intel® FPGA IP

1.1. HDMI Intel® FPGA IP Design Guidelines

The HDMI Intel® FPGA interface has Transition Minimized Differential Signaling (TMDS) data and clock channels. The interface also carries a Video Electronics Standards Association (VESA) Display Data Channel (DDC).

The TMDS channels carry video, audio, and auxiliary data. The DDC is based on I2C protocol. The HDMI Intel® FPGA IP core uses the DDC to read Extended Display Identification Data (EDID) and exchange configuration and status information between an HDMI source and sink.

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