Turbo Intel® FPGA IP User Guide

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ID 683734
Date 9/30/2022
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Document Table of Contents
Document Table of Contents x
1. About the Turbo Intel® FPGA IP 2. Getting Started with the Turbo Intel® FPGA IP 3. Parameter Settings 4. Turbo Intel® FPGA IP Functional Description A. Turbo IP User Guide Document Archives 5. Document Revision History for Turbo Intel® FPGA IP User Guide
1. About the Turbo Intel® FPGA IP x
1.1. Turbo Intel® FPGA IP Features 1.2. Turbo Intel® FPGA IP Device Family Support 1.3. Turbo IP Performance and Resource Utilization 1.4. Turbo Code Licensing Disclaimer 1.5. Release Information
2. Getting Started with the Turbo Intel® FPGA IP x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. IP Catalog and Parameter Editor 2.3. Specifying the IP Core Parameters and Options 2.4. Simulating Intel® FPGA IP Cores 2.5. Simulating the IP with the RTL Simulator 2.6. Simulating the Turbo IP with the C-Model 2.7. Simulating the Turbo IP with MATLAB
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode 2.1.2. Turbo IP Timeout Behavior
2.3. Specifying the IP Core Parameters and Options x
2.3.1. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition)
4. Turbo Intel® FPGA IP Functional Description x
4.1. Turbo Encoder 4.2. Turbo Decoder 4.3. 4.4. Turbo Throughput
4.1. Turbo Encoder x
4.1.1. Turbo Encoder Data Format 4.1.2. Turbo Encoder Latency Calculation
4.2. Turbo Decoder x
4.2.1. Turbo Decoder Data Format Output 4.2.2. CRC24A or CRC24B Early Termination 4.2.3. Decoder Latency Calculation 4.2.4. Error Correction Performance for the Turbo Decoder
1. About the Turbo Intel® FPGA IP
2. Getting Started with the Turbo Intel® FPGA IP
3. Parameter Settings
4. Turbo Intel® FPGA IP Functional Description
A. Turbo IP User Guide Document Archives
5. Document Revision History for Turbo Intel® FPGA IP User Guide

4.2.1. Turbo Decoder Data Format

Table 12.  Turbo Decoder Output Data Ordering for a Block of Size K N is the width of the input LLRs.
Input Data sink_data
3N - 1 down to 2N 2N - 1 down to N N - 1 down to 0
0 Z ’0 Z 0 X 0
1 Z ’1 Z 1 X 1
... ... ... ...
K - 1 Z ’ K - 1 Z K - 1 X K - 1
K X K + 1 Z K X K
K + 1 Z K + 2 X K + 2 Z K + 1
K + 2 X ’ K + 1 Z ’ K X ’ K
K + 3 Z ’ K + 2 X ’ K + 2 Z ’ K + 1

The Turbo decoder requires all data to be in the log-likelihood format. The connected system must provide soft information, including parity 1 and parity 2 bit sequences according to the following equation:

L(x) = log[P(x=1)/(x=0)]

The log-likelihood value is the logarithm of the probability that the received bit is a 1, divided by the probability that this bit is a 0. It is represented as a two’s complement number. A value of zero indicates equal probability of a 1 and a 0, which you should use for depuncturing. The decoder does not use the most negative two’s complement number, which means the representation is balanced.

Table 13.  Four-bit Mapping Input Values
Input (3 downto 0) Value
0111 Most likelihood of a 1
... ...
0001 Lowest likelihood of a 1
0000 Equal probability of a 0 or 1
1111 Lowest likelihood of a 0
... ...
1001 Most likelihood of a 0
1000 Not used

Output

The number of output bits can be 1 or 8 bits. For 1 bit, the ordering is: X 0, X 1, X 2, . . . . X K-1

Table 14.  8-bit Output Data Ordering
Output Order source_data
7 6 5 4 3 2 1 0
1 X 7 X 6 X 5 X 4 X 3 X 2 X 1 X 0
2 X 15 X 14 X 13 X 12 X 11 X 10 X 9 X 8
... ... ... ... ... ... ... ... ...
K/8 X K - 1 X K – 2 X K – 3 X K – 4 X K – 5 X K – 6 X K – 7 X K – 8
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