External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 9/26/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.1.5.11. status for RLDRAM 3

PHY calibration status interface

Table 149.  Interface: statusInterface type: Conduit
Port Name Direction Description
local_cal_success Output When high, indicates that PHY calibration was successful
local_cal_fail Output When high, indicates that PHY calibration failed