6.6. Programming the FPGA Device
To complete this section of the tutorial, you must have installed one of the following supported design examples:
- PCIe-based design example for Arria® 10 devices
This design example requires the Intel® Programmable Acceleration Card (PAC) with Arria® 10 GX FPGA board.
- PCIe-based design example for Agilex™ 7 devices
This design example requires the Terasic* DE10-Agilex Development Board.
For installation instructions, see FPGA AI Suite Installation Overview.
The PCIe-based design examples requires a runtime layer that must be compiled before the design is usable. The runtime for the design examples typically needs to be compiled only once. However, a new FPGA bitstream must be generated whenever any of the following parameters change:
- Number of IP instances built in the design example.
- PCIe-based design example for Arria® 10 devices supports 1 or 2 instances.
- PCIe-based design example for Agilex™ 7 devices supports up to 4 instances.
- Configuration of the IP architecture (as specified by a .arch file)
- Quartus fitter seed (or any other "try-harder" compilation options)
Depending on your design example, follow the instructions in one of the following sections:
Programming the Agilex™ 7 Device ( Terasic* DE10-Agilex Development Board)
To program the DE10-Agilex-B2E2 board required by the PCIe-based design example for Agilex™ 7 devices:
- Build the runtime with the following commands:
cd $COREDLA_WORK/runtime rm -rf build_Release ./build_runtime.sh -de10_agilex
- Program the bitstream onto the FPGA device with the following commands:
jtagdir=$COREDLA_WORK/runtime/build_Release/fpga_jtag_reprogram bitsdir=$COREDLA_WORK/demo/bitstreams $jtagdir/fpga_jtag_reprogram $bitsdir/AGX7_Performance.sof curarch=$COREDLA_ROOT/example_architectures/AGX7_Performance.arch
The bitstream completely reprograms the board, which causes it to disconnect from the PCIe bus. The board is kept accessible with the $COREDLA_WORK/runtime/fpga_jtag_reprogram tool.
Precompiled bitstreams are provided in the $COREDLA_WORK/demo/bitstreams/ directory. Some bitstreams instantiate a large IP, while others instantiate a small IP. There are also differences in which bitstreams support which neural networks. For details, refer to the FPGA AI Suite IP Reference Manual .
Programming the Arria® 10 Device ( Intel® PAC with Arria® 10 GX FPGA)
To program the Intel® PAC with Arria® 10 GX FPGA hardware used by the PCIe-based design example for Arria® 10 devices:
- Build the runtime with the following commands:
cd $COREDLA_WORK/runtime rm -rf build_Release ./build_runtime.sh
- Program the bitstream onto the FPGA device with the following commands:
fpgaconf -v $COREDLA_WORK/demo/bitstreams/A10_Performance.gbs curarch=$COREDLA_ROOT/example_architectures/A10_Performance.arch
The bitstream contains only the AFU. In this case, the AFU consists of the FPGA AI Suite IP and some interface logic to connect it to the FIM. The FIM, which is the logic delivered as part of the BSP responsible for the interfaces like the memory interface and PCIe interface, is already on the FPGA device.
Precompiled bitstreams are provided in the $COREDLA_WORK/demo/bitstreams/ directory. Some bitstreams instantiate a large IP, while others instantiate a small IP. There are also differences in which bitstreams support which neural networks. For details, refer to the FPGA AI Suite IP Reference Manual .