GTS Serial Lite IV Intel® FPGA IP Design Example User Guide

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ID 813973
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the GTS Serial Lite IV Intel® FPGA IP Design Example User Guide 2. Quick Start Guide 3. Detailed Description for GTS Serial Lite IV Design Example 4. Document Revision History for the GTS Serial Lite IV Intel® FPGA IP Design Example User Guide
2. Quick Start Guide x
2.1. Design Example Block Diagram 2.2. Software Requirements 2.3. Generating the Design 2.4. Compiling and Simulating the Design
2.3. Generating the Design x
2.3.1. Design Example Parameters 2.3.2. Directory Structure
3. Detailed Description for GTS Serial Lite IV Design Example x
3.1. Features 3.2. Design Example Components 3.3. Simulation 3.4. Error Handling 3.5. Link Debugging Sequence
3.2. Design Example Components x
3.2.1. Traffic Generator 3.2.2. Traffic Checker 3.2.3. DCFIFO
1. About the GTS Serial Lite IV Intel® FPGA IP Design Example User Guide
2. Quick Start Guide
3. Detailed Description for GTS Serial Lite IV Design Example
4. Document Revision History for the GTS Serial Lite IV Intel® FPGA IP Design Example User Guide

2.4. Compiling and Simulating the Design

The design example testbench simulates your generated design.
  1. Change the working directory to <example_design_directory>/ed_sim.
  2. Run the simulation script for the simulator of your choice.
    Table 5.  Testbench Simulation Scripts
    Simulator File Directory Command
    Questa* Intel® FPGA Edition <variation name>intel_sl4_gts_0_example_design/ed_sim source run_mentor.tcl
    Note: source evaluates a file or resource as a Tcl script (Tools - Tcl - Execute - Macro).
    QuestaSim*
    VCS* <variation name>intel_sl4_gts_0_example_design/ed_sim sh run_vcs.sh
    VCS* MX <variation name>intel_sl4_gts_0_example_design/ed_sim sh run_vcsmx.sh
    Xcelium* <variation name>intel_sl4_gts_0_example_design/ed_sim sh run_xcelium.sh
    Riviera-PRO* <variation name>intel_sl4_gts_0_example_design/ed_sim riviera -do run_riviera.do
  3. When the simulation is complete, you can now analyze the results and verify the design. A successful simulation ends with the following message, "Test Passed."
Note: LANES, Streaming Mode, and RSFEC Enable may vary according to their parameters.
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