AN 539: Test Methodology of Error Detection and Recovery using CRC in Intel FPGA Devices

ID 683075
Date 8/09/2019
Public
Document Table of Contents

1.1.4.2. EMR for Arria® V, Cyclone® V, and Stratix® V Devices

Figure 3. EMR Contents for Arria® V, Cyclone® V, and Stratix® V Devices
Table 3.  Error Type Represented in the EMR for Arria® V, Cyclone® V, and Stratix® V Devices
Error Type Description
Bit 4 Bit 3 Bit 1 Bit 0
0 0 0 0 No CRC error is identified.
0 0 0 1 Location of a single error is identified.
0 0 1 0 Location of a double-adjacent bit error is identified.
1 1 1 1 Uncorrectable errors.
Others Invalid.