AN 539: Test Methodology of Error Detection and Recovery using CRC in Intel FPGA Devices

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ID 683075
Date 8/09/2019
Public
Document Table of Contents
Document Table of Contents x
1. Test Methodology of Error Detection and Recovery using CRC in Intel® FPGA Devices
1. Test Methodology of Error Detection and Recovery using CRC in Intel® FPGA Devices x
1.1. Functional Description 1.2. Error Correction 1.3. Using the Error Detection CRC Feature 1.4. Error Injection 1.5. Modifying Single-Device .jam Files for Use in a Multi-Device JTAG Chain 1.6. Running .jam Files with the Intel® Quartus® Prime Jam Tools 1.7. Document Revision History for AN 539: Test Methodology of Error Detection and Recovery using CRC in Intel® FPGA Devices
1.1. Functional Description x
1.1.1. Configuration Error Detection 1.1.2. User Mode Error Detection 1.1.3. Error Detection Pin 1.1.4. Error Message Register 1.1.5. Error Detection Timing
1.1.4. Error Message Register x
1.1.4.1. EMR for Arria® II, Stratix® III, and Stratix® IV Devices 1.1.4.2. EMR for Arria® V, Cyclone® V, and Stratix® V Devices
1.3. Using the Error Detection CRC Feature x
1.3.1. Error Detection using User Logic 1.3.2. Error Detection using an External Host
1.3.1. Error Detection using User Logic x
1.3.1.1. Detecting CRC Errors through the CRC_ERROR Output Signal 1.3.1.2. Unloading the EMR through User Logic 1.3.1.3. Accessing the Error Detection Block through User Logic 1.3.1.4. User Logic Control Block 1.3.1.5. User Logic Control Block Signals
1.3.2. Error Detection using an External Host x
1.3.2.1. Detecting a CRC Error through the CRC_ERROR Output Signal 1.3.2.2. Unloading the EMR using an External Host
1.4. Error Injection x
1.4.1. Fault Injection Register 1.4.2. Error Injection using the EDERROR_INJECT JTAG Instruction 1.4.3. Clearing Fault Injection Register
1.4.1. Fault Injection Register x
1.4.1.1. Fault Injection for Arria® II, Stratix® III, and Stratix® IV Devices 1.4.1.2. Fault Injection for Arria® V, Cyclone® V, and Stratix® V Devices
1.4.2. Error Injection using the EDERROR_INJECT JTAG Instruction x
1.4.2.1. Injecting Single-Bit Error for Arria® II, Stratix® III, and Stratix® IV 1.4.2.2. Injecting Single-Bit Error for Arria® V, Stratix® V, and Cyclone® V Devices
1. Test Methodology of Error Detection and Recovery using CRC in Intel® FPGA Devices

1.5. Modifying Single-Device .jam Files for Use in a Multi-Device JTAG Chain

The .jam file codes in this document are meant for a single-device JTAG chain. To use these codes in a multi-device JTAG chain, add instruction register (IR) and data register (DR) lengths of the devices in the chain other than the .jam file's target device.
  1. Check the instruction register lengths of all the other devices in the JTAG chain.
    • IR length:
      • Intel® FPGA and CPLD devices: 10
      • Hardware processor system (HPS) in Intel® SoC FPGA devices: 4
    • DR length in any device: 1
  2. Locate the PROCEDURE EXECUTE line in the .jam file codes and add codes in the following steps to new lines after it.
  3. If there are devices in the chain before the target device, add the following codes: 
    POSTIR <total IR length before the target device>;
POSTDR <total DR length before the target device>;
  4. If there are devices in the chain after the target device, add the following codes: 
    PREIR <total IR length after the target device>;
PREDR <total DR length after the target device>;

Other Devices Exist in JTAG Chain Before or After Target Device

For each example chain, add the codes after the PROCEDURE EXECUTE line:

  • Download cable TDI → other device 1 (IR=10) → target device → download cable TDO:
    POSTIR 10;
POSTDR 1;
  • Download cable TDI → target device → other device 1 (IR=10) → download cable TDO:
    PREIR 10;
PREDR 1;
  • Download cable TDI → target device → other device 1 (IR=10) → other device 2 (IR=10) → download cable TDO:
    PREIR 20;
PREDR 2;
  • Download cable TDI → other device 1 (IR=4) → target device → other device 2 (IR=10) → download cable TDO:
    POSTIR 4;
POSTDR 1;
PREIR 10;
PREDR 1;
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