L- and H-Tile Avalon® Streaming and Single Root I/O Virtualization (SR-IOV) Intel® FPGA IP for PCI Express* User Guide

ID 683111
Date 4/23/2024
Public
Document Table of Contents

9.4.9. BFM Configuration Procedures

The BFM configuration procedures are available in altpcietb_bfm_rp_gen5_x16.sv. These procedures support configuration of the Root Port and Endpoint Configuration Space registers.

All Verilog HDL arguments are type integer and are input‑only unless specified otherwise.