AN 916: JESD204C Intel® FPGA IP and ADI AD9081/AD9082 MxFE* Interoperability Report for Intel® Stratix® 10 E-Tile Devices

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ID 683157
Date 6/22/2020
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Document Table of Contents
Document Table of Contents x
1. JESD204C Intel® FPGA IP and ADI AD9081/AD9082 MxFE* Hardware Checkout Report for Intel® Stratix® 10 E-Tile Devices
1. JESD204C Intel® FPGA IP and ADI AD9081/AD9082 MxFE* Hardware Checkout Report for Intel® Stratix® 10 E-Tile Devices x
1.1. Hardware Requirements 1.2. Hardware Setup 1.3. JESD204C Intel® FPGA IP and ADC Hardware Checkout 1.4. JESD204C Intel® FPGA IP and DAC Hardware Checkout 1.5. Document Revision History for AN 916: JESD204C Intel® FPGA IP and ADI AD9081/AD9082 MxFE* Interoperability Report for Intel® Stratix® 10 E-Tile Devices 1.6. Appendix
1.3. JESD204C Intel® FPGA IP and ADC Hardware Checkout x
1.3.1. ADC Hardware Checkout Methodology 1.3.2. JESD204C Intel® FPGA IP and ADC Configurations 1.3.3. ADC Test Results 1.3.4. ADC Test Result Comment
1.3.1. ADC Hardware Checkout Methodology x
1.3.1.1. Receiver Data Link Layer 1.3.1.2. Receiver Transport Layer
1.3.1.1. Receiver Data Link Layer x
1.3.1.1.1. Sync Header Alignment 1.3.1.1.2. Extended Multiblock Alignment (EMBA)
1.4. JESD204C Intel® FPGA IP and DAC Hardware Checkout x
1.4.1. DAC Hardware Checkout Methodology 1.4.2. JESD204C Intel® FPGA IP and DAC Configurations 1.4.3. DAC Test Results 1.4.4. DAC Test Result Comment
1.4.1. DAC Hardware Checkout Methodology x
1.4.1.1. Transmitter Data Link Layer 1.4.1.2. Transmitter Transport Layer
1.4.1.1. Transmitter Data Link Layer x
1.4.1.1.1. TX_RST
1. JESD204C Intel® FPGA IP and ADI AD9081/AD9082 MxFE* Hardware Checkout Report for Intel® Stratix® 10 E-Tile Devices

1.4.3. DAC Test Results

The following table shows the results for test cases TXRST.1 and TXTL.1 with subclass 0 and FCLK_MULP = 2.

Table 10.  Result for Test Cases TXRST.1 and TXTL.1
Test No. L M F E Lane Rate (Mbps) DAC Rate (Msps) Link Clock (MHz) Result
1 8 8 2 1 16000 1939.39394 121.212121 PASS

The following figure shows the Signal Tap waveform of the PRBS pattern data transmitted to FPGA transmitter transport layer.

Figure 7. PRBS Data Pattern Diagram

The following figure shows the result of the pattern checker at output data of DAC transport layer.

Figure 8. DAC PRBS Checker Result
Level Two Title