AN 916: JESD204C Intel® FPGA IP and ADI AD9081/AD9082 MxFE* Interoperability Report for Intel® Stratix® 10 E-Tile Devices

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ID 683157
Date 6/22/2020
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Document Table of Contents
Document Table of Contents x
1. JESD204C Intel® FPGA IP and ADI AD9081/AD9082 MxFE* Hardware Checkout Report for Intel® Stratix® 10 E-Tile Devices
1. JESD204C Intel® FPGA IP and ADI AD9081/AD9082 MxFE* Hardware Checkout Report for Intel® Stratix® 10 E-Tile Devices x
1.1. Hardware Requirements 1.2. Hardware Setup 1.3. JESD204C Intel® FPGA IP and ADC Hardware Checkout 1.4. JESD204C Intel® FPGA IP and DAC Hardware Checkout 1.5. Document Revision History for AN 916: JESD204C Intel® FPGA IP and ADI AD9081/AD9082 MxFE* Interoperability Report for Intel® Stratix® 10 E-Tile Devices 1.6. Appendix
1.3. JESD204C Intel® FPGA IP and ADC Hardware Checkout x
1.3.1. ADC Hardware Checkout Methodology 1.3.2. JESD204C Intel® FPGA IP and ADC Configurations 1.3.3. ADC Test Results 1.3.4. ADC Test Result Comment
1.3.1. ADC Hardware Checkout Methodology x
1.3.1.1. Receiver Data Link Layer 1.3.1.2. Receiver Transport Layer
1.3.1.1. Receiver Data Link Layer x
1.3.1.1.1. Sync Header Alignment 1.3.1.1.2. Extended Multiblock Alignment (EMBA)
1.4. JESD204C Intel® FPGA IP and DAC Hardware Checkout x
1.4.1. DAC Hardware Checkout Methodology 1.4.2. JESD204C Intel® FPGA IP and DAC Configurations 1.4.3. DAC Test Results 1.4.4. DAC Test Result Comment
1.4.1. DAC Hardware Checkout Methodology x
1.4.1.1. Transmitter Data Link Layer 1.4.1.2. Transmitter Transport Layer
1.4.1.1. Transmitter Data Link Layer x
1.4.1.1.1. TX_RST
1. JESD204C Intel® FPGA IP and ADI AD9081/AD9082 MxFE* Hardware Checkout Report for Intel® Stratix® 10 E-Tile Devices

1.2. Hardware Setup

An Intel® Stratix® 10 TX SI Development Kit (Production Rev B Edition) is used with the Analog Devices AD9081 daughter card module installed to the FMC+ connector of the development board.

  • The AD9081 EVM derives power from the FMC+ pins.
  • The FPGA reference clock is supplied by a pulse generator through an SMA cable.
  • The pulse generator provides device clock to the MxFE on the AD9081 EVB through an SMA cable.
Figure 1. Hardware Setup

The following system-level diagram shows how the different modules connect in this design.

Figure 2. System Diagram

In this setup, where LMF = 882, the data rate of the transceiver lanes is 24.75 Gbps. The pulse generator is used to provide reference clock to the clock generator Si53311. The core PLL reference clock and the transceiver reference clock is generated by the clock generator Si53311.

For FCLK_MULP=2, the core PLL generates 187.5 MHz link clock and 375 MHz frame clock. The pulse generator also provides the AD9081 device clock of 3000 MHz. The SPI master in the FPGA programs the AD9081 registers through the 4 wire SPI interfaces via FMC pins. The converters operate in a single JESD link in all configurations with a maximum of 8 lanes.

Level Two Title