Intel® Programmable Acceleration Card (PAC) with Intel® Arria® 10 GX FPGA Data Sheet

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ID 683226
Date 10/26/2020
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Overview 3. System Compatibility 4. Mechanical Information 5. Thermal Specifications 6. FPGA Interface Manager 7. Board Management Controller 8. PLDM Commands for the Board Management Controller A. Regulatory Information B. References C. Revision History
2. Overview x
2.1. Views of the Intel® PAC with Intel® Arria® 10 GX FPGA 2.2. Overview of Product Features
2.2. Overview of Product Features x
2.2.1. Intel® Arria® 10 GX FPGA 2.2.2. On-Board Memory 2.2.3. Interfaces and Dimensions 2.2.4. Software 2.2.5. Power 2.2.6. CPLD 2.2.7. QSFP+ Switches QSFP+ SerDes 2.2.8. Control and Support
2.2.8. Control and Support x
2.2.8.1. PCIe Overview 2.2.8.2. Board Management Controller Overview
4. Mechanical Information x
4.1. Air Duct Disassembly
5. Thermal Specifications x
5.1. Thermal Test Performance Results
6. FPGA Interface Manager x
6.1. Updating the FIM
7. Board Management Controller x
7.1. Features 7.2. Device Peripheral Table 7.3. Updating the BMC Configuration and Firmware
7.1. Features x
7.1.1. BMC Voltage and Thermal Handling
8. PLDM Commands for the Board Management Controller x
8.1. I2C/SMBus Address 8.2. Supported SMBus Commands 8.3. Supported MCTP Commands 8.4. Supported PLDM Commands 8.5. Defined Platform Descriptor Records 8.6. Sensor and Threshold Information
8.3. Supported MCTP Commands x
8.3.1. MCTP Control Messages
8.4. Supported PLDM Commands x
8.4.1. PLDM Base Specification Commands 8.4.2. PLDM for Platform Monitoring and Control Specification Commands
1. Introduction
2. Overview
3. System Compatibility
4. Mechanical Information
5. Thermal Specifications
6. FPGA Interface Manager
7. Board Management Controller
8. PLDM Commands for the Board Management Controller
A. Regulatory Information
B. References
C. Revision History

2.2.7. QSFP+

The Intel® PAC with Intel® Arria® 10 GX FPGA has a QSFP+ cage on the front panel which supports 40GbE or four 10GbE.

The table below details the Intel® -supported connectors. For volume deployment, you must use Intel-validated QSFP+ cables.

Successful functioning of 40GbE and 10GbE requires appropriate physical medium attachment (PMA) settings. Run the provided PMA settings script as detailed in the 10Gbps Ethernet Accelerator Functional Unit (AFU) Design Example User Guide or 40Gbps Ethernet Accelerator Functional Unit (AFU) Design Example User Guide.

Table 1.  QSFP+ Support for the Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA
  Model Number
Intel® Ethernet QSFP+ 1-meter direct attach cable (DAC) twinaxial cables XLDACBL1
Intel® Ethernet QSFP+ 3-meter direct attach cable (DAC) twinaxial cables XLDACBL3
Intel® Ethernet QSFP+ short reach (SR) optic module E40GQSFPSR
Intel® Ethernet QSFP+ 1-meter Passive Breakout Cable X4DACBL1
Intel® Ethernet QSFP+ 3-meter Passive Breakout Cable X4DACBL3

Switches

Intel has used the following switches in their validation configuration.

Table 2.  Intel-Validated Switches
Ethernet AFU Switch Brand Switch Model Number
40 Gbps Ethernet Dell* Z9100-ON
Extreme Networks* x870-32C
Mellanox* SN2700
10 Gbps Ethernet Cisco* Nexus N9K-C93180YC-EX
Lenovo* 8272
Dell* 8024F

QSFP+ SerDes

The QSFP+ interface has four Serializer/Deserializer (SerDes) lanes connected directly to the FPGA.

Related Information
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