AN 712: Altera JESD204B MegaCore Function and ADI AD9625 Hardware Checkout Report

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ID 683294
Date 6/13/2016
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Document Table of Contents
Document Table of Contents x
1. Altera JESD204B IP Core and ADI AD9625 Hardware Checkout Report
1. Altera JESD204B IP Core and ADI AD9625 Hardware Checkout Report x
1.1. Hardware Requirements 1.2. Hardware Setup for Stratix V Advanced Systems Development Kit 1.3. Hardware Setup for Arria 10 GX FPGA Development Kit 1.4. Hardware Checkout Methodology 1.5. JESD204B IP Core and AD9625 Configurations 1.6. Test Results 1.7. Test Result Comments 1.8. AN 712 Document Revision History
1.4. Hardware Checkout Methodology x
1.4.1. Receiver Data Link Layer 1.4.2. Receiver Transport Layer 1.4.3. Descrambling 1.4.4. Deterministic Latency (Subclass 1)
1.4.1. Receiver Data Link Layer x
1.4.1.1. Code Group Synchronization (CGS) 1.4.1.2. Initial Frame and Lane Synchronization
1. Altera JESD204B IP Core and ADI AD9625 Hardware Checkout Report

1.2. Hardware Setup for Stratix V Advanced Systems Development Kit

A Stratix V Advanced Systems Development Kit is used with the ADI AD9625 daughter card module attached to the FMC connector of the development board.

  • The AD9625 EVM derives power through the development kit FMC connector.
  • The ADC device clock is supplied by external clock source card through the SMA connector on the AD9625 EVM.
  • The AD9625 divides the sampling clock by four and supplies this divided clock through its DIVCLK pins to the FPGA.
  • For subclass 1, the FPGA generates SYSREF for the JESD204B IP core as well as the AD9625 device.
Figure 1.  Hardware Setup


Figure 2. System-Level Block Diagram


The system-level block diagram shows how the different modules connect in this design. In the setup depicted above, LMF=811 and the data rate of transceiver lanes is 6.25 Gbps. An external clock source card provides 2.5 GHz sampling clock to the AD9625 device and the ADC supplies 625 MHz FPGA device clock through its DIVCLK pin.

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