Agilex™ 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series

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ID 683301
Date 4/01/2024
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Document Table of Contents
Document Table of Contents x
Agilex™ 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series
Agilex™ 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series x
Electrical Characteristics Switching Characteristics Configuration Specifications I/O Timing Programmable IOE Delay Glossary Document Revision History for the Agilex 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series
Electrical Characteristics x
Operating Conditions
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot and Undershoot Voltage Recommended Operating Conditions DC Characteristics I/O Standard Specifications
Recommended Operating Conditions x
Recommended Operating Conditions E-Tile Transceiver Power Supply Recommended Operating Conditions P-Tile Transceiver Power Supply Recommended Operating Conditions R-Tile Transceiver Power Supply Recommended Operating Conditions F-Tile Transceiver Power Supply Recommended Operating Conditions HPS Power Supply Recommended Operating Conditions
DC Characteristics x
Supply Current and Power Consumption I/O Pin Leakage Current Bus Hold Specifications OCT Calibration Accuracy Specifications OCT Without Calibration Resistance Tolerance Specifications Pin Capacitance Internal Weak Pull-Up Resistor Hysteresis Specifications for Schmitt Trigger Input
I/O Standard Specifications x
Single-Ended I/O Standards Specifications Single-Ended SSTL, HSTL, HSUL, and POD I/O Reference Voltage Specifications Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications Differential SSTL, HSTL, and HSUL I/O Standards Specifications Differential POD I/O Standards Specifications Differential I/O Standards Specifications
Switching Characteristics x
Core Performance Specifications Periphery Performance Specifications E-Tile Transceiver Performance Specifications P-Tile Transceiver Performance Specifications R-Tile Transceiver Performance Specifications F-Tile Transceiver Performance Specifications HPS Performance Specifications
Core Performance Specifications x
Clock Tree Specifications I/O PLL Specifications DSP Block Specifications Memory Block Specifications Local Temperature Sensor Specifications Remote Temperature Diode Specifications Voltage Sensor Specifications
Periphery Performance Specifications x
LVDS SERDES Specifications DPA Lock Time Specifications LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications Memory Standards Supported DLL Range Specifications Memory Output Clock Jitter Specifications
E-Tile Transceiver Performance Specifications x
E-Tile Transceiver Performance E-Tile Transceiver Reference Clock Specifications E-Tile Transmitter Specifications E-Tile Receiver Specifications
P-Tile Transceiver Performance Specifications x
P-Tile Transceiver Performance P-Tile Transceiver Reference Clock Specifications P-Tile Transmitter Specifications P-Tile Receiver Specifications
R-Tile Transceiver Performance Specifications x
R-Tile Transceiver Performance R-Tile Transceiver Reference Clock Specifications R-Tile Transmitter Specifications R-Tile Receiver Specifications
F-Tile Transceiver Performance Specifications x
F-Tile Transceiver Performance F-Tile Transceiver Reference Clock Specifications F-Tile Transmitter Specifications F-Tile Receiver Specifications F-Tile Electrical Compliance
HPS Performance Specifications x
HPS Clock Performance HPS Internal Oscillator Frequency HPS PLL Specifications HPS Cold Reset HPS SPI Timing Characteristics HPS SD/MMC Timing Characteristics HPS USB UPLI Timing Characteristics HPS Ethernet Media Access Controller (EMAC) Timing Characteristics HPS I2C Timing Characteristics HPS NAND Timing Characteristics HPS Trace Timing Characteristics HPS GPIO Interface HPS JTAG Timing Characteristics HPS Programmable I/O Timing Characteristics
Configuration Specifications x
General Configuration Timing Specifications POR Specifications External Configuration Clock Source Requirements JTAG Configuration Timing AS Configuration Timing Avalon® Streaming (Avalon®-ST) Configuration Timing Configuration Bit Stream Sizes
Agilex™ 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series

F-Tile Receiver Specifications

Table 70.  F-Tile FHT Receiver Electrical Specifications For specification status, see the Data Sheet Status table
Parameter Symbol Description Min Typical Max Unit
Receiver input eye specifications VRX-DIFF-PKPK Receiver input differential peak-to-peak voltage Closed eye — 1,200 mVdiff-pkpk
VRX-CM-DC Receiver input DC common-mode voltage91 100 — 900 mV
VRX-MAX Receiver input maximum voltage — — 1,200 mV
VRX-MIN Receiver input minimum voltage –200 — — mV
TRX-DDJ Receive input signal data dependent jitter (inter-symbol interference) — — 1 UIpkpk
TRX-RJ Receive input random jitter — — 0.15 UIpkpk
TRX-PJ Receive input periodic jitter (at high frequency) — — 0.05 UIpkpk
TRX-TJ Receive input total jitter (DDJ + RJ + PJ) — — 1  UIpkpk
Equalizer specifications FPPM-OFFSET Tolerable data frequency offset –200 — 200 ppm
Receiver return loss ZRL-DIFF-DC Receiver differential DC return loss — — 10 dB
ZRL-DIFF-NYQ Receiver differential return loss at Nyquist frequency (FBAUD/2) — — 6 dB
ZRL-CM Receiver common-mode return loss below 10 GHz — — 6 dB
Receiver DC impedance RDIFF-DC DC differential receive impedance 80 100 120 Ω
RCM-DC DC common-mode receive impedance 20 25 30 Ω
Table 71.  F-Tile FGT Receiver Electrical Specifications For specification status, see the Data Sheet Status table
Parameter Symbol Description Min Typical Max Unit
Receiver input eye specifications VRX-DIFF-PKPK Receiver input differential peak-to-peak voltage92 Closed eye — 1,200 mV
VRX-MAX Receiver input maximum voltage93 — — 1 V
VRX-MIN Receiver input minimum voltage93 –0.3 — — V
VRX-CM-DC Receiver input DC common-mode voltage94 0 — 700 mV
TRX-RJ Receive input random jitter — — 0.15 UIpkpk
TRX-PJ Receive input periodic jitter (at high frequency) — — 0.05 UIpkpk
Insertion loss specifications IINS-LOSS-56Gb/s Insertion loss at 56 Gbps PAM42/BER <10–4 — — 30 dB
IINS-LOSS-53Gb/s Insertion loss at 53 Gbps PAM42/BER <10–4 595 — — dB
IINS-LOSS-30Gb/s Insertion loss at 32 Gbps NRZ96 /BER <10–12 — — 30 dB
IINS-LOSS-25Gb/s Insertion loss at 25.78125 Gbps NRZ96/ BER <10–12 — — 30 dB
Receiver return loss ZRL-DIFF-DC Receiver differential DC return loss — — 12 dB
ZRL-DIFF-NYQ Receiver differential return loss at Nyquist frequency (FBAUD/2) — — 6 dB
ZRL-CM Receiver common-mode return loss below 10 GHz — — 6 dB
Receiver DC impedance RDIFF-DC DC differential receive impedance 65 85 102 Ω
80 100 120 Ω
RCM-DC DC common-mode receive impedance 20 25 30 Ω
Receiver signal detection97 VIDLE-THRESH Receiver signal detect input voltage threshold 75 120 175 mVdiff-pkpk
91 Referenced to RX GND. This specification is also supported before mode configuration.
92 This is supported when the receiver is powered and configured, powered and unconfigured, or unpowered.
93 VRX_MAX and VRX_MIN are before and after configuration.
94 The specified common-mode range is supported when the receiver is powered and configured, powered and unconfigured, or unpowered. This specification is also supported before mode configuration. If squelch detect is used, receiver DC input common-mode voltage should be within 200 mV to 300 mV. Otherwise, use AC coupling capacitors on board.
95 The minimum insertion loss specification assumes a PAM4 transmitter with 800 mVppd. For transmitters with output amplitude adjustment capabilities and can reduce output amplitude to below 800 mVppd, this minimum insertion loss can be further relaxed.
96 COM compliant package and channel.
97 Receiver signal detection values in this table are applicable to PCIe* and similar standards, such as SATA, where a clock pattern like PCIe* EIEOS 500 MHz clock pattern is used.
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