Low Latency Ethernet 10G MAC Intel® FPGA IP Release Notes

Download PDF
ID 683308
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
Low Latency Ethernet 10G MAC Intel® FPGA IP (intel_eth_em10g32) Release Notes Low Latency Ethernet 10G MAC Intel® FPGA IP (alt_em10g32) Release Notes
Low Latency Ethernet 10G MAC Intel® FPGA IP (intel_eth_em10g32) Release Notes x
Low Latency Ethernet 10G MAC Intel® FPGA IP (intel_eth_em10g32) v2.0.0
Low Latency Ethernet 10G MAC Intel® FPGA IP (alt_em10g32) Release Notes x
Low Latency Ethernet 10G MAC Intel® FPGA IP v22.0.4 Low Latency Ethernet 10G MAC Intel® FPGA IP v22.0.3 Low Latency Ethernet 10G MAC Intel® FPGA IP v22.0.1 Low Latency Ethernet 10G MAC Intel® FPGA IP v22.0.0 Low Latency Ethernet 10G MAC Intel® FPGA IP v20.1.0 Low Latency Ethernet 10G MAC Intel® FPGA IP v20.0.0 Low Latency Ethernet 10G MAC Intel® FPGA IP v19.3.1 Low Latency Ethernet 10G MAC Intel® FPGA IP v19.3.0 Low Latency Ethernet 10G MAC Intel® FPGA IP v19.2.0 Low Latency Ethernet 10G MAC Intel® FPGA IP v19.1 Low Latency Ethernet 10G MAC Intel® FPGA IP v18.1 Low Latency Ethernet 10G MAC Intel® FPGA IP v18.0 Intel FPGA Low Latency Ethernet 10G MAC IP Core v17.1 Update 1 Intel FPGA Low Latency Ethernet 10G MAC IP Core v17.1 Low Latency Ethernet 10G MAC IP Core v17.0 Low Latency Ethernet 10G MAC IP Core v16.1 Low Latency Ethernet 10G MAC IP Core v16.0 Low Latency Ethernet 10G MAC IP Core v15.1 Low Latency Ethernet 10G MAC IP Core v15.0 Low Latency Ethernet 10G MAC IP Core v14.1 Low Latency Ethernet 10G MAC IP Core v14.0 Arria 10 Edition Low Latency Ethernet 10G MAC IP Core v14.0 Low Latency Ethernet 10G MAC IP Core v13.1 Arria 10 Edition Low Latency Ethernet 10G MAC IP Core v13.1
Low Latency Ethernet 10G MAC Intel® FPGA IP (intel_eth_em10g32) Release Notes
Low Latency Ethernet 10G MAC Intel® FPGA IP (alt_em10g32) Release Notes

Low Latency Ethernet 10G MAC IP Core v16.0

Table 18.  v16.0 May 2016
Description Impact
  • Support for 1G/2.5G/5G/10G (USXGMII) operating modes.
  • Design Examples for Low Latency 10G Ethernet MAC:
    • Added the following design examples:
      • 10G USXGMII Ethernet
      • 10GBase-R
      • 1G/2.5G Ethernet
      • 1G/2.5G Ethernet with 1588
      • 1G/2.5G/10G Ethernet
    • Added support for custom development board.
    • Enhanced reset scheme for the following design examples, where the MAC reset is decoupled from the PHY reset:
      • 10M/100M/1G/10G Ethernet
      • 10M/100M/1G/10G Ethernet with 1588
      • 1G/10G Ethernet
      • 1G/10G Ethernet with 1588
    • Added a Signal Tap file (.stp) for the following designs:
      • 10GBase-R Register Mode
      • 10M/100M/1G/10G Ethernet
      • 10M/100M/1G/10G Ethernet with 1588
      • 1G/10G Ethernet
      • 1G/10G Ethernet with 1588
 —
Related Information
Level Two Title