Low Latency Ethernet 10G MAC Intel® FPGA IP Release Notes

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ID 683308
Date 4/01/2024
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Low Latency Ethernet 10G MAC Intel® FPGA IP (intel_eth_em10g32) Release Notes Low Latency Ethernet 10G MAC Intel® FPGA IP (alt_em10g32) Release Notes
Low Latency Ethernet 10G MAC Intel® FPGA IP (intel_eth_em10g32) Release Notes x
Low Latency Ethernet 10G MAC Intel® FPGA IP (intel_eth_em10g32) v2.0.0
Low Latency Ethernet 10G MAC Intel® FPGA IP (alt_em10g32) Release Notes x
Low Latency Ethernet 10G MAC Intel® FPGA IP v22.0.4 Low Latency Ethernet 10G MAC Intel® FPGA IP v22.0.3 Low Latency Ethernet 10G MAC Intel® FPGA IP v22.0.1 Low Latency Ethernet 10G MAC Intel® FPGA IP v22.0.0 Low Latency Ethernet 10G MAC Intel® FPGA IP v20.1.0 Low Latency Ethernet 10G MAC Intel® FPGA IP v20.0.0 Low Latency Ethernet 10G MAC Intel® FPGA IP v19.3.1 Low Latency Ethernet 10G MAC Intel® FPGA IP v19.3.0 Low Latency Ethernet 10G MAC Intel® FPGA IP v19.2.0 Low Latency Ethernet 10G MAC Intel® FPGA IP v19.1 Low Latency Ethernet 10G MAC Intel® FPGA IP v18.1 Low Latency Ethernet 10G MAC Intel® FPGA IP v18.0 Intel FPGA Low Latency Ethernet 10G MAC IP Core v17.1 Update 1 Intel FPGA Low Latency Ethernet 10G MAC IP Core v17.1 Low Latency Ethernet 10G MAC IP Core v17.0 Low Latency Ethernet 10G MAC IP Core v16.1 Low Latency Ethernet 10G MAC IP Core v16.0 Low Latency Ethernet 10G MAC IP Core v15.1 Low Latency Ethernet 10G MAC IP Core v15.0 Low Latency Ethernet 10G MAC IP Core v14.1 Low Latency Ethernet 10G MAC IP Core v14.0 Arria 10 Edition Low Latency Ethernet 10G MAC IP Core v14.0 Low Latency Ethernet 10G MAC IP Core v13.1 Arria 10 Edition Low Latency Ethernet 10G MAC IP Core v13.1
Low Latency Ethernet 10G MAC Intel® FPGA IP (intel_eth_em10g32) Release Notes
Low Latency Ethernet 10G MAC Intel® FPGA IP (alt_em10g32) Release Notes

Low Latency Ethernet 10G MAC Intel® FPGA IP v18.0

Table 13.  v18.0 May 2018
Description Impact
Renamed Low Latency Ethernet 10G MAC IP core to Low Latency Ethernet 10G MAC Intel® FPGA IP core as per Intel rebranding. —
Added support for the following operation modes for Stratix® 10 devices:
  • 10M/100M/1G/2.5G/5G/10G (USXGMII)
  • 10M/100M/1G/2.5G/5G/10G (USXGMII) with IEEE 1588v2 feature
 —
Added support for the following operation mode for Arria® 10 devices:

  • 10M/100M/1G/2.5G/5G/10G (USXGMII)

 —
Added new parameter for LL Ethernet 10G MAC Intel® FPGA IP:
  • TX and RX datapath Reset/Default to Enable:

    Turning on this parameter disables TX and RX datapath during startup or CSR reset.

 —
Design Examples for Low Latency 10G Ethernet MAC Intel® FPGA IP:
  • Added the following design example for Stratix® 10 devices:
    • 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet
    • 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet with IEEE 1588v2 feature
  • Added the following design example for Arria® 10 devices:
    • 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet
  • Added the following design example for Cyclone® 10 GX devices:
    • 10GBASE-R Ethernet
 —
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