AN-811: Using the Avery BFM for PCI Express Gen3x16 Simulation on Intel® Stratix® 10 Devices

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ID 683477
Date 1/23/2018
Public
Document Table of Contents
Document Table of Contents x
AN-811: Using the Avery BFM for PCI Express Gen3x16 Simulation on Intel® Intel® Stratix® 10 Devices Create the Example Design Setup the Simulation Environment Run the Simulation View Results Document Revision History
AN-811: Using the Avery BFM for PCI Express Gen3x16 Simulation on Intel® Intel® Stratix® 10 Devices x
Software Requirements Design Components High-level Overview of Steps
Setup the Simulation Environment x
Download and Extract the Avery Simulation Scripts Create the Avery BFM File List Create the Example Design File List Configure the Avery BFM Testbench Top-level File
Create the Avery BFM File List x
VCS ModelSim
Create the Example Design File List x
VCS ModelSim
Configure the Avery BFM x
VCS ModelSim
Run the Simulation x
VCS ModelSim
AN-811: Using the Avery BFM for PCI Express Gen3x16 Simulation on Intel® Intel® Stratix® 10 Devices
Create the Example Design
Setup the Simulation Environment
Run the Simulation
View Results
Document Revision History

Testbench Top-level File

Testbench top-level file modification is performed automatically, and a new top-level file (pcie_example_design_tb.sv) is included with the Avery simulation scripts.

It has the same name as the old top-level, but instantiates the Avery BFM in place of the Intel FPGA BFM. Additionally, the file format is changed from Verilog to System Verilog to facilitate integration with the Avery BFM.

For the VCS simulator, you should have added the new top-level to the file list in VCS. For the ModelSim simulator, the script, mentor.do, compiles the new top-level separately after compiling all other design files.

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